I applied through other source and the process took 3 weeks - interviewed at AMD in February 2014.
Interview Details – Came to know about the position through LinkedIn from a senior manager at AMD. It took 3 weeks for scheduling a phone interview.
Interview Question – Questions were from resume.
How will you verify a 32 bit ALU unit having 2 inputs is working fine for all 2^32 * 2^32 combinations? Answer Question
I interviewed at AMD in March 2014.
Interview Details – First round is phone interview .Most of question are general question .Such as your understanding about hardware and software . Difference between C and C++
How to solve the setup time and hold time violation .
Cache replace policy and pipeline problems .
After questions is general introduction about their company location ,size ,group and so on
Interview Question – How to verify your design ？about testbench design ... Answer Question
Very Easy Interview
I applied through an employee referral and the process took 4 weeks - interviewed at AMD in November 2013.
Interview Details – Got a call through employee referral.
Interview Question – Interview was really based just on resume Answer Question
I applied online and the process took 6 days - interviewed at AMD in August 2013.
Interview Details – I applied the job via company website and got the chance to be phone interviewed the same day I applied...... I was in a vacation at that time!!!! Anyway, we set up a time and did an hour interview four days later.... The questions covers all the stuffs from hardware to software. They are not difficult individually, however, it requires you know every aspect of the computer. My answers to those questions are ..... not bad, according to the recruiter. But I do fail some of them. Finally, I cannot get the chance to do a onsite interview. I lose a good opportunity!!!!
Interview Question – The process of changing page when there is a page fault. Very detail! Answer Question
Interviewed at AMD
Interview Details – Phone interview: First described what this team does and what this position for. Then asked some questions on my resume, about my educations and experience. He let me choose one of favorite project and describe to him. Then asked a question, which can be considered as several sub questions.
Interview Question – While synthesizing memory(SRAM), how to estimate the area, delay and power? What can you do to solve time violation. Answer Question
I applied through an employee referral and the process took 2+ weeks - interviewed at AMD in May 2013.
Interview Details – I got the call for telephonic interview through referral. Phone interview was around 45 - 60 min. After the getting through the phone screen, was invited for onsite.
The onsite was from 9am - 4pm, with 6 1:1 45min sessions and lunch with the manager.
Interview Question – Phone Screen:
>Difference b/w latch and flip flop
>Clock domain crossing; synchronizers, how they are placed wrt floor planning
>Explain what is IR drop and EM and ways to reduce it
>Inverter sizing; wrt mobility, drive strengths, matching charge/ discharge delays, rise/ fall times
>Verilog blocking and non-blocking statements and what do they realise in hw
>Dynamic power dissipation and ways to reduce it
>Static power dissipation and ways to reduce it; RBB/ FBB, multiple Vt devices
>A buffer ckt, wherein the o/p of inv1, voltage is equal to the switching threshold of inv2, now what is the o/p of the buffer; static power dissipation, dc path question
>Realise AND/OR/NAND logic using 2:1 mux
>What is setup/ hold time violations; meta-stability issues
>How to overcome setup/ hold time violations
> crosstalk and how will you reduce it
>Nmos pull up, Pmos pull down structure with rising step input. Was asked to draw the output pattern and explain the functioning of the circuit and also to predict what it's used as.
>asked to draw transistor level diag of 2 i/p nand gate and explain how i size it
>was given a logical path and i had to size the devices using logical effort
>asked to draw a transistor level diag of flip flop and point out the setup and hold nodes
>2 i/p dynamic nand gate -> cascade of 2 stages connected directly w/o a domino inv; asked to draw the wave patter at final out
>contd: now with domino inv; asked how big it should be
>contd: level restorer; concepts of full keeper, whether it can be used in the given case
>concepts of clock feed through, charge sharing, back gate coupling
>questions from my resume regarding the projects that i have worked on and also some of asic tools related to PD
>how do you compare two values; what logic you will use
>timing optimization wrt given logic structure; had to re-arrange the logic blocks and also make use of alternate gates to implement the logic and meet the timing considerations
>explain crosstalk; what is aggressor and victim, how will you reduce it
>some questions on clock tree synthesis; was given a scenario with inv's of specific drive strengths and asked to place them accordingly on the given grid
>given a <63:0> 2 i/p and gate, where will you position the gate in a rectangle block taking into consideration crosstalk; floor planning wrt crosstalk issues
>asked about async fifo (from resume); corner cases and working
>asked to implement a boolean logic using k-map minimization
>pseudo code explaining blocking and non-blocking usage, taking example of flip flop
>cache - write back, write through caches, cache replacement policies, messi protocol, cache organization - direct mapped, set associative
>specific questions from my resume
>setup/ hold time violations
>given scenario: if receiving flop is delayed wrt launching flop, what timing parameter is violated and how to rectify it
>contd: if launching flop is delayed wrt receiving flop, again what is affected and how to overcome the issue
>wrt my resume (PLL design), few questions regarding charge pump design
>signal integrity issues - cross talk, IR drop, EM with specific scenarios and ways to reduce
>2 i/p nor gate with sizing and its layout; multi fingering
>ways to reduce interconnect delay Answer Question
I applied online - interviewed at AMD in August 2013.
Interview Details – phone interview, asked about C++ programming and concept of computer architecture.
1. write c code to check prime number
2. write c code to detect different elements in two array
3. verilog blocking and non-blocking
4. different b/w c and verilog
5. different b/w template and virtual funciton
6. what is cache, cache coherence
7. different b/w stack and heap
8. what is interrupt
Interview Question – difference bw template and virtual function Answer Question
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