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AMD Graduate Design Engineer/Physical Design Interview Questions

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Graduate Design Engineer/Physical Design Interview

Anonymous Interview Candidate in Austin, TX
Anonymous Interview Candidate in Austin, TX
Application Details

I applied through an employee referral. The process took 2+ weeksinterviewed at AMD in May 2013.

Interview Details

I got the call for telephonic interview through referral. Phone interview was around 45 - 60 min. After the getting through the phone screen, was invited for onsite.

The onsite was from 9am - 4pm, with 6 1:1 45min sessions and lunch with the manager.

Interview Questions
  • Phone Screen:
    >Difference b/w latch and flip flop
    >Clock domain crossing; synchronizers, how they are placed wrt floor planning
    >Explain what is IR drop and EM and ways to reduce it
    >Inverter sizing; wrt mobility, drive strengths, matching charge/ discharge delays, rise/ fall times
    >Verilog blocking and non-blocking statements and what do they realise in hw
    >Dynamic power dissipation and ways to reduce it
    >Static power dissipation and ways to reduce it; RBB/ FBB, multiple Vt devices
    >A buffer ckt, wherein the o/p of inv1, voltage is equal to the switching threshold of inv2, now what is the o/p of the buffer; static power dissipation, dc path question
    >Realise AND/OR/NAND logic using 2:1 mux
    >What is setup/ hold time violations; meta-stability issues
    >How to overcome setup/ hold time violations
    > crosstalk and how will you reduce it

    Onsite:
    Round #1:
    >Nmos pull up, Pmos pull down structure with rising step input. Was asked to draw the output pattern and explain the functioning of the circuit and also to predict what it's used as.
    >asked to draw transistor level diag of 2 i/p nand gate and explain how i size it
    >was given a logical path and i had to size the devices using logical effort
    >asked to draw a transistor level diag of flip flop and point out the setup and hold nodes
    >2 i/p dynamic nand gate -> cascade of 2 stages connected directly w/o a domino inv; asked to draw the wave patter at final out
    >contd: now with domino inv; asked how big it should be
    >contd: level restorer; concepts of full keeper, whether it can be used in the given case
    >concepts of clock feed through, charge sharing, back gate coupling

    Round #2:
    >questions from my resume regarding the projects that i have worked on and also some of asic tools related to PD
    >how do you compare two values; what logic you will use
    >timing optimization wrt given logic structure; had to re-arrange the logic blocks and also make use of alternate gates to implement the logic and meet the timing considerations
    >explain crosstalk; what is aggressor and victim, how will you reduce it
    >some questions on clock tree synthesis; was given a scenario with inv's of specific drive strengths and asked to place them accordingly on the given grid
    >given a <63:0> 2 i/p and gate, where will you position the gate in a rectangle block taking into consideration crosstalk; floor planning wrt crosstalk issues
    >asked about async fifo (from resume); corner cases and working

    ROund #3:
    >asked to implement a boolean logic using k-map minimization
    >pseudo code explaining blocking and non-blocking usage, taking example of flip flop
    >cache - write back, write through caches, cache replacement policies, messi protocol, cache organization - direct mapped, set associative
    >specific questions from my resume

    Round #4:
    >setup/ hold time violations
    >given scenario: if receiving flop is delayed wrt launching flop, what timing parameter is violated and how to rectify it
    >contd: if launching flop is delayed wrt receiving flop, again what is affected and how to overcome the issue
    >wrt my resume (PLL design), few questions regarding charge pump design

    Round #5:
    >signal integrity issues - cross talk, IR drop, EM with specific scenarios and ways to reduce
    >2 i/p nor gate with sizing and its layout; multi fingering
    >ways to reduce interconnect delay
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