Glassdoor is your free inside look at Cadence Design Systems interview questions and advice. All 10 interview reviews posted anonymously by Cadence Design Systems employees and interview candidates.
Cadence Design Systems Interview Questions & Reviews
Getting the Interview 10 Interviews
Interview Experience 8 Ratings
Senior Member of Technical Staff at Cadence Design Systems
No Offer – Interviewed in San Jose, CA Aug 2011 – Reviewed Apr 20, 2013
Interview Details –
A position on timing analysis.
Three phone interviews. On-site interview after three phone interviews. Eight on-site interviewers.
Asked questions on fundamental circuit theories (~30%) and coding/complexity analysis (~70%).
Interview Question –
A question on convergence theory.
A question regarding root-finding algorithm (secant method etc).
Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Design/Verification Engineer at Cadence Design Systems
No Offer – Interviewed in Raleigh, NC – Reviewed Nov 18, 2012
Interview Details – campus, + on site
Interview Question – design a FSM based on a given bus protocol Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Application Engineer at Cadence Design Systems
No Offer – Interviewed in San Jose, CA Jun 2010 – Reviewed Jun 11, 2010
Interview Details – A short Phone Interview with manager, followed by on site interview. The people at cadence are very nice and professional. It was a nice experience.
Interview Questions
- Static timing analysis Answer Question
- Logic synthesis Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Application Engineer at Cadence Design Systems
No Offer – Interviewed in Santa Clara, CA Sep 2009 – Reviewed Nov 3, 2009
Interview Details – We had talked about my resume, and the work I had done previously with my former company. The interviewer went into details of the Cadence tool for which the AE would be responsible for if he were to get the job. In the end, they found other interviewees with more experience with that particular Cadence Tool.
Interview Question – Describe some of the common errors you come across while using the cadence tool View Answer
Helpful Interview?
Yes |
No
Problem with this interview?
Software Engineer at Cadence Design Systems
No Offer – Interviewed in Noida (India) Aug 2010 – Reviewed Apr 28, 2013
Interview Details – I was called for an interview. Where I was asked to solve a written test containing software,hardware and aptitude questions. It was a 90 minutes test. As I couldn't clear the test, I don't know any further about the process.
Interview Question – Few technical questions regarding hardware was very difficult.. and the Aptitude test was very tricky... Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Hardware Engineer at Cadence Design Systems
No Offer – Reviewed Dec 6, 2012
Interview Details – phone interview with a senior manager..was briefed on some of the technologies that CDS is working on. Later was asked some brief tech questions from circuit design, logic design fundamentals
Interview Question – why does one use a header and not a footer for power gating View Answer
Helpful Interview?
Yes |
No
Problem with this interview?
Software Engineer at Cadence Design Systems
No Offer – Interviewed in Noida (India) Jul 2012 – Reviewed Oct 3, 2012
Interview Details – written then 2 interviews and then HR interview. interview consisted of basic digital and c c++ questions.they also asked about static time analysis and sequential circuits.
Interview Question – puzzles about defective balls and balance. it had 12 balls and one of them was defected so to find it in minimum no of weighings. View Answer
Helpful Interview?
Yes |
No
Problem with this interview?
Timing Analysis Engineer at Cadence Design Systems
No Offer – Interviewed in Jan 2012 – Reviewed Feb 22, 2012
Interview Details – I got 2 phone screen in consequence 2 weeks(2012 Jan), but I didn't do very well, so no further contact till now. He ask about STA flow and some basic FlipFlop and Latch issue and set up/hold time and some concept of C++ when implement a graph. It's a timing analysis group and the interviewer is the group leader. In conclude, this kind of group will focus on graph Algorithm like DFS and coding ability like C++ and of course some digital design concept like I mention above. Hope it help!
Interview Question – What kind of data structure should we use to implement a graph in C++ View Answer
Helpful Interview?
Yes |
No
Problem with this interview?
Application Engineer at Cadence Design Systems
No Offer – Interviewed in Feb 2011 – Reviewed Jun 21, 2011
Interview Details – Unscheduled telephone call: I was not expecting the call and was in the middle of another project. The interview started by asking a technical question about systemverilog - write code in your head - image the design. ---- I refuse to recite coding standards. Actually, I refer to book and the internet if I cannot remember a systemverilog rule - duh!
Interview Question – Design an OVM interface for --- using systemverilog? View Answer
Helpful Interview?
Yes |
No
Problem with this interview?
Engineering at Cadence Design Systems
No Offer – Interviewed in New Delhi (India) Jul 2010 – Reviewed Aug 30, 2010
Interview Details –
Good quality question.
Interviewer was to much conservative to accept the innovation or learning opportunities.
Interview Questions
- Multithreading Answer Question
- UML Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
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