Intel Corporation
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Intel Corporation Component Design Engineer Interview Questions & Reviews

Updated Jun 6, 2014
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Accepted Offer

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Average Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

I applied online and the process took 2 weeks - interviewed at Intel Corporation in November 2009.

Interview Details – Phone screen.. Followed by 1:1s with 6 team members covering various areas like computer architecture, verilog, logic design, and scripting.

Interview Question – Linked list, hash table   Answer Question

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Very Easy Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

I applied through college or university and the process took 2 days - interviewed at Intel Corporation in November 2010.

Interview Details – The interviews for the Nand group are very simple, based on logic design device physics and simple circuit questions. Its a cake walk to clear the same. People are amiable, however the technical experience that you get out of this job is very little compared to working in GPU, CPU teams.

Interview Question – Voltage at the end of a stack of pass-transistors   Answer Question

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No Offer

Neutral Experience

Average Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

The process took a day - interviewed at Intel Corporation in April 2012.

Interview Details – The hiring manager e-mailed me about the phone screening, which I expected to be about what I did on my projects but turned out to be a technical interview about the position. Consisted of basic questions on memory, caches, Virtual memory, What happens on write, TLB, DMA and Some C questions regarding pointers, arrays and linked lists.

Interview Question – What is the difference between linked lists and arrays ...?   Answer Question

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Positive Experience

Average Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

I applied through college or university and the process took 2 days - interviewed at Intel Corporation in May 2011.

Interview Details – I submitted my resume to Intel employees who'd come to collect resumes and talk about Intel. They were from the graphics group and wanted software/hardware engineers to work on Intel's integrated chips.
I got a mail saying they were interested in my profile and asked for my availability for a phone screen.
The phone screen tested:
i) My C skills: String manipulation, Pointers
ii) Graphics knowledge: The 3D pipeline, briefly describing each of the stages, depth/alpha testing, OpenGL vs DirectX (some very trivial stuff, if you've taken a graphics course)
iii) Debugging: Visual Studio experience, debugging skills (straight-forward and not expecting much detail).

I was selected for the on-site, and there, I had 5 1:1 interviews with several managers.
The questions were related to:
i) C, C++ : Lots of questions regarding pointer manipulation, type casting, const usage in member functions of classes, string manipulation
ii) Image processing : I was asked to rotate an image by 90 degrees
iii) Graphics: Again, 3D pipeline, general questions about pixel shaders, why they're needed, depth/alpha testing, finding intersection of lines/rectangles, OpenGL vs DirectX (testing if i knew anything about it).
iv) Software Engineering: Tried to ask me about design patterns via a question, but I really didn't know enough about it.

Interview Questions

Negotiation Details – The pay is pretty decent, considering it was not the Bay area, but a lot lesser than normal software companies.
They gave me a joining bonus on negotiation and I accepted.

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Positive Experience

Average Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

I applied through college or university and the process took 2+ weeks - interviewed at Intel Corporation in January 2010.

Interview Details – I was an intern there and so I got the interview through my university contact at Intel.
Phone screen by the hiring manager asking about my intention to work there.
On site group interview consisted of 6 interviews ranging from a presentation by the group director and 4 technical interviews followed by a wrap up by the hiring manager.
Technical interview consisted of Programming (C, C++), Logic, Circuits( CMOS, Demorgans theorem etc), VLSI design concepts.
Had lunch with the team I would be working with midway through the interview.

Interview Question – Nothing unexpected. Typical questions for an electrical engineer. Should be prepared to answer how CMOS logic works, programming basic routines in C++, logic gates and simplifying the signals etc   Answer Question

Negotiation Details – Did not negotiate. Accepted the offer given.

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Declined Offer

Positive Experience

Average Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

The process took a day - interviewed at Intel Corporation in February 2012.

Interview Details – I was called onsite for the interview. The hiring manger was very friendly and made me comfortable from the very begining. He also offered me coffee. These are the few questions which he asked me -
1. how to minimize a boolean expression
2. k-map optimization
3. how to divide a frequency
4. draw a divide by 2 counter,divide by 4 counter
5.timing diagrams of the counters.
6.master-slave flip-flop
7.setup time,hold time definitions, violations, and how to fix them
8.verilog- diffrnce b/w blocking and non-blocking,design a D Flipflop

Interview Question – How to fix the hold-time violation after the chip was fabricated?   View Answer

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Positive Experience

Average Interview

Component Design Engineer Interview

Component Design Engineer
Chandler, AZ

I applied through other source and the process took a day - interviewed at Intel Corporation in January 2009.

Interview Details – I was interviewed in February of 2004 for a position @ Intel in Chandler, Az. I was phone screened initially and then flown out for the formal interview process which consisted of 5 1:1 sessions with the teams design engineers. Since I was coming from college directly the questions consisted mostly of text book Q&A, situational questioning, and inquiries into my internships. I don't remember anything being too difficult and everyone was quite friendly. I've "heard horror stories" about how other companies perform their interviews but in my experience and with the 30+ interviews I've performed myself since I've been at Intel, this was nothing like those.

Interview Questions

  • I was asked to draw the circuit diagram of a comparator and then describe how it functions on the circuit level.   View Answer
  • I was asked what options one might have to rectify a max timing path.   View Answer

Negotiation Details – I actually did not negotiate at all. In 2004 the job market was tough, companies had their pick of the litter, and this was the best offer I was given so I didn't see the need to mess around. Only other offer I had was for a company located about 30 miles outside Boston (MUCH higher living expenses) for less pay. This was kind of a no brainer for me.

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Accepted Offer

Positive Experience

Difficult Interview

Component Design Engineer Interview

Component Design Engineer
Hudson, MA

The process took 2 weeks - interviewed at Intel Corporation in July 2011.

Interview Details – Received 1 technical phone screen with questions derived from my resume with a few higher level what-if questions. The interviewer was on time with our agreed upon time for the phone conversation. The next step took a little longer because of the July 4th holiday weekend, but was scheduled about 3 weeks after the initial screen. The onsite interview consisted of 3 1hr 1:1s very technical in nature designed to find my breaking point. An off-site lunch with the hiring manager was nice and casual. Compensation expectations were discussed on the ride back to campus. 3 more 1hr 1:1s were scheduled with a different design group and were equally as challenging. I was impressed with the caliber of people that interviewed me and felt like I did very well answering the questions.

Interview Questions

  • In Verilog what is the difference between a blocking and non-blocking statement?   View Answer
  • Explain to me what an early clock is and on what edges you would like to clock the data on to avoid race conditions.   Answer Question

Negotiation Details – There was no negotiation in the offer other than the start date. I wanted a break between jobs and to enjoy the rest of summer and got it. The base pay was slightly less than my previous job, but the whole compensation package was better.

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Accepted Offer

Positive Experience

Difficult Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

I applied through a recruiter and the process took a day - interviewed at Intel Corporation in June 2011.

Interview Details – Phone interview lasted for 1 hour. Questions were as follows: derive equation from FSM, K-maps, equation reduction using De-morgans law,pipelining and hazards, inverter working, how Vth varied with temp, SRAM working. 2 weeks later was called for onsite interview. Consisted of 4 rounds.
1st round: questions related to system verilog, projects, design FSM from waveforms and conditions given. C code for converting binary to octal.
2nd round: Given a black box and some conditions and asked to design a digital system. Design FF's. Given verilog code and asked to design gate level diagram.
3rd round: Questions related to computer architecture. Asked project related questions.Cache write policies, write back, write through, PCI,PCI-E, arbitration, how to get faster circuits, latest INTEL chipset architecture. Remember all the questions were indirect.Logical questions.
4th round: Timing analysis. Slew, fanout, design flow, setup and hold circuit analysis. Circuit analysis. All questions were logical,none direct.
Hope this helps!!
All the interviewer's were friendly and co-operative. It was basically like a discussion rather than question and answer session.

Interview Question – C code to convert binary to octal   Answer Question

Negotiation Details – No negotiation since RCG position

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No Offer

Neutral Experience

Easy Interview

Component Design Engineer Interview

Component Design Engineer
Folsom, CA

The process took 1 week - interviewed at Intel Corporation in February 2011.

Interview Details – How to remove setup and hold time violations?

Interview Question – What are the setup and hold violations and how to remove them?   Answer Question

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