Linear Technology

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Linear Technology Interview Questions

Updated Sep 25, 2014
Updated Sep 25, 2014
9 Interview Reviews

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  1.  

    Design Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Application Details

    I applied online. The process took 1+ weekinterviewed at Linear Technology in February 2014.

    Interview Details

    One of its director contacted me through email. Then we had a phone talk about some general but philosophy questions about analog circuit design. One week's later, I had a phone interview with one of his senior engineers about several technical questions.

    Interview Questions
    • A circuit like current mirror but quite strange. Because instead of copying current from a diode connected transistor to current source, the circuit intends to copy the current back.   View Answer
    No Offer
    Positive Experience
    Difficult Interview
  2. 1 person found this helpful  

    Test Engineer Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Interview Details

    The interview process was extremely professional from start to finish. Initial contact was made at a career fair and an offer to come to their facility for an interview was extended at that time. The interview lasted about 4 hours, with a one hour overview of the company/position and a tour of the facility, followed by about 2 1/2 hours of one-on-one interviews with two supervisors, and then a 1/2 hour recap.

    Interview Questions
    • The questions were all technical-based to determine the level of understanding of basic analog circuit design.   Answer Question
    No Offer
  3. 1 person found this helpful  

    Process Integration Engineer Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Application Details

    I applied online. The process took 2+ weeksinterviewed at Linear Technology in December 2013.

    Interview Details

    Email first to make appointment for interview, then telephone interview.

    Interview Questions
    No Offer
    Neutral Experience
    Difficult Interview
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  5. 1 person found this helpful  

    Test Engineer Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Application Details

    I applied through a recruiter. The process took 4+ weeksinterviewed at Linear Technology in November 2013.

    Interview Details

    Overall, Interview process went well. Got a phone interview, and then an onsite interview. Onsite was 1 on 1 interview for about 1 hour each session. Interview took the whole day, maybe 8 hour or so. I was exhausted. Tested on fundamental circuit theories and also digital circuits theories. Very nice, bright, and professional interviewers. Would definitely enjoy working at the facility, but did not receive any follow up after the onsite.

    Interview Questions
    No Offer
    Positive Experience
    Average Interview
  6. 1 person found this helpful  

    Process Integration Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Application Details

    I applied through college or university – interviewed at Linear Technology in March 2013.

    Interview Details

    Phone interview for around an hour. Asked about physics of BJT and MOSFET, process of fabrication.

    Interview Questions
    • The questions are very detailed, so make sure to read up before the interview.   Answer Question
    No Offer
    Difficult Interview
  7.  

    Analog IC Design Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Application Details

    I applied through college or university – interviewed at Linear Technology in February 2013.

    Interview Details

    On campus interview and it was normal talking for 30 minutes and technical questions for 15 minutes. The guy was very nice and he was giving me hints if I am stuck.

    Interview Questions
    • Do a detail DC sweep of a n-channel MOSFET and Graph.   View Answer
    No Offer
    Positive Experience
    Average Interview
  8. 3 people found this helpful  

    Layout Designer Interview

    Anonymous Interview Candidate in Cary, NC
    Anonymous Interview Candidate in Cary, NC
    Application Details

    I applied online. The process took a dayinterviewed at Linear Technology in February 2011.

    Interview Details

    Application date was Jan 14, email follow-up by site manager Feb 10, to discuss position. After the initial discussion, I requested to talk in person, and the manager agreed I could come in the following week. It was not clear at the time that I had a full-blown interview, because a formal interview was not mentioned nor was the time required for the interview (5 hours) or the number of people I would talk to. Perhaps a communication lapse? No matter, I was happy to have the opportunity.

    The interview started at 9:00 am and I left the premises at about 2:15 pm.

    The interview consisted of a series of one-on-ones with the site manager, a design engineer, a design team manager, a design team leader and two layout designers.

    The manager asked preliminary questions to clear up areas of confusion or inconsistency on my resume, then we proceeded to a conference room where I was asked technical questions about analog layout. The topics included: Lateral BJT device design, MOSFET device design, CMOS device design, BiCMOS device design, JFET device design, basic thin film resistor design, MOS capacitor design, isolation wells, reverse bias (depletion isolation) design practices, fundamentals of parasitic latch-up devices, simple NMOS and PMOS design with one or two transistors, identification of devices by symbol and the obligatory Ohm's law. All designers used color layout plots to ask questions, asking me to identify basic devices and features, such as BJTs and location of well ties.

    Impressions: Design engineers very competent, asked questions like grad students giving ungraded pop quiz to undergrad lab students. So, they were easy going, but to the point.

    Advice: Know that they use LATERAL BJT devices. If you are unfamiliar with analog physical design or are rusty, get ahold of a picture or a working design and study it. Practice identifying NPN, PNP, isolation wells and all well and substrate ties. They use analogy symbols for MOS devices, so if you are used to dealing with the simplified digital depictions, study up on the various symbols used in analog.

    After the designers, it was a sit-down test at a workstation with a layout designer standing and looking over my shoulder. I was asked to use Cadence XL to layout two simple designs implemented in PCELLS. The first design used BJTs, the second design used CMOS devices.

    Impressions: Stressful, cold, clinical assessment of CAD tool familiarity and layout design skill.

    Advice: Know Cadence XL, and do not make any mistakes related to layout. Lay out the CMOS circuit tight, as if it was a standard cell.

    Sandwich lunch followed with the site manager and another layout designer. Site manager generously paid for all. After that it was a low-key one-on-one with the second layout designer where the discussion was left rather open-ended.

    The interview was completed by a wrap-up discussion with the site manager. I was informed via email the morning after that I had not been selected.

    Office was in an older building (20 years) and workers were clearly responsible for their own workspace cleanliness and neatness, so this varied according to particular office or cubicle. Kitchenette was standard with coffee, tea, hot water, sink and fridge. Restroom (Men's) was clean.

    Overall impression: Small office, few levels of hierarchy, very casual but busy with lots of work.

    Interview Questions
    • Given this side view of a partial BJT design, can you complete the design and identify the base, emitter and collector?   View Answer
    No Offer
    Neutral Experience
    Difficult Interview
  9.  

    Design Engineer Interview

    Anonymous Interview Candidate in Boston, MA
    Anonymous Interview Candidate in Boston, MA
    Application Details

    The process took a dayinterviewed at Linear Technology in February 2011.

    Interview Details

    He asked basic questions, one current mirror matching problem, one circuit transfer function, one noise related quesiton

    Interview Questions
    No Offer
    Neutral Experience
    Average Interview
  10. 1 person found this helpful  

    Analog IC Design Intern Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Application Details

    The process took 4 daysinterviewed at Linear Technology in November 2011.

    Interview Details

    Four 45 minute interviews at their location

    Interview Questions
    No Offer
    Negative Experience
    Average Interview

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