Cadence Design Application Engineer Jobs & Careers

Cadence Designs – Bangalore (India)

As a member of Field Application Engineering team at Cadence this Application… Application engineer will interact, educate, consult and provide solutions to…

Cadence Designs – 16 days ago

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Cadence Designs – Austin, TX +2 locations

As an Application Engineer (AE) in Cadences Verification Division you will consult with customers on Advanced Verification Methodologies and Technologies with a focus on SystemVerilog UVM implementations. You will work with leading edge customers deploying the industrys most advanced verification methodologies and technologies. In this role you will develop your skills in verification environment architecture, implementation and debug leveraging SystemVerilog and UVM. The role will allow you to experience many application areas such as Graphics, Networking, Mobile and processor verification. Position Requirements Experience: 7plus years as a Verification Engineer. Required to have experience in creating Verification environments utilizing SystemVerilog, Vera, e or SystemC/C++ . Strong team player with a wiliness to learn new skills and methodologies. Track record of successfully verifying complex ASICs is also required. Languages: SystemVerilog, Specman, …

Cadence Designs – 17 days ago

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Cadence Designs – Irvine, CA

As an Advanced Verification Application Engineer (AE) in Cadences Verification Division you will consult with customers on deployment of Cadences industry leading Verification IP portfolio. Your duties will include leading the technical discovery process and demonstrating Cadences VIP capabilities via integration into customers real verification environments. You will work with leading edge customers and will have the opportunity to develop your skills in standard protocols such as PCIE, USB, Ethernet, etc. This role will allow you to experience many application areas such as Graphics, Networking, Mobile and processor verification. Position Requirements: Knowledge of standard protocols such as PCIe, Ethernet, USB3.0, MIPI, AMBA is required Proven ability with methodologies such as OVM/VMM/UVM or ERM is also desirable Strong team player with a wiliness to learn new skills and methodologi …

Cadence Designs – 3 days ago

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Cadence Designs – Irvine, CA

As an Application Engineer (AE) in Cadences Verification Division you will consult with customers on Advanced Verification Methodologies and Technologies with a focus on SystemVerilog UVM implementations. You will work with leading edge customers deploying the industrys most advanced verification methodologies and technologies. In this role you will develop your skills in verification environment architecture, implementation and debug leveraging SystemVerilog and UVM. The role will allow you to experience many application areas such as Graphics, Networking, Mobile and processor verification. Position Requirements Experience: 2-3 years as a Verification Engineer. Required to have experience in creating Verification environments utilizing SystemVerilog, Vera, e or SystemC/C++ . Strong team player with a wiliness to learn new skills and methodologies. Track record of successfully verifying complex ASICs is also required. Languages: SystemVerilog, Specman, Ve …

Cadence Designs – 7 days ago

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