Getting an Interview
Getting an Interview
Interviews for Top Jobs at AMD
- Software Engineer (15)
- Design Engineer II (14)
- Design Engineer (13)
- Co-Op Engineer (11)
- Verification Engineer (9)
- Intern (9)
- Senior Design Engineer (9)
- Member of Technical Staff (8)
- Engineer (7)
- Product Development Engineer (6)
- Engineering (6)
- Marketing Manager (6)
- Co-Op (5)
- Design Verification Engineer (4)
- Senior Product Development Engineer (3)
- Senior Verification Engineer (3)
- Physical Design Engineer (3)
- Hardware Engineer (3)
- Program Manager (3)
- Senior Engineer (2)
- Test Engineer (2)
- Senior Software Development Engineer (2)
- Senior Software Engineer (2)
- ASIC/Layout Design Engineer II (2)
- Circuit Designer (2)
- Senior Manager (2)
- Product Development Engineer II (2)
- Project Manager (2)
- Analog Design Engineer (2)
- ASIC Design Engineer (2)
Design Verification Engineer Interview
I applied online. The process took 2+ months – interviewed at AMD (Boxborough, MA) in December 2011.
I had 2 phone interviews over 4 weeks. Generally discussed about current research projects. I was invited to meet the team in Boxborough, MA in December. I had around 7 personal interviews including one during lunch. The interviewers were pretty good asked questions on microarchitecture, projects, object oriented concepts, verification and logic design. I was informed by the recruiter that they'll have a decision by next day. I was told that the team was interested in my candidacy but wanted to conduct one more interview over Skype. I didn't here back from them for about 4 weeks when they told me that they have already identified a other candidate. Overall it was very poor and unprofessional job by the team manager and the recruiter.
Other Interview Reviews for AMD
Design Verification Engineer InterviewNo OfferPositive ExperienceAverage Interview
The process took a week – interviewed at AMD (Sunnyvale, CA) in April 2012.
Phone interview was pretty basic questions about comp arch, object oriented concepts. Onsite interview consisted of 6 rounds technical + 1 HR interview. Questions were mainly comp arch, cache coherency, pipelining techniques. A few questions on verilog, system verilog, perl, assembly language.
- How would you verify a write-back 4-way set associative cache using assembly language programming. 1 Answer
Design Verification Engineer InterviewAccepted OfferPositive ExperienceAverage Interview
I applied through college or university – interviewed at AMD (Toronto, ON (Canada)) in November 2010.
Just one on-site interview before hiring. Was interviewed by two engineers on the team. Was for most parts a typical software engineering interview, only superficial questions about hardware. No explicit coding questions but lots of questions about how you would code it. After receiving the offer, I was also invited to a tour of the company's buildings and to meet the rest of the team.
- How would you verify a that a basic flip-flop works? Answer Question
Design Verification Engineer InterviewNo OfferPositive ExperienceEasy Interview
I applied online. The process took 1 day – interviewed at AMD (Austin, TX) in February 2012.
After applying online, received phone call a few days later from a lower-level employee with a couple of years experience. The phone interview was completely technical in nature, with no personality or leadership questions. Got invited to be flown down for an on-site interview, but was already in town, so was able to interview the next day. On-site interview was four 45-minute interviews with employees of different divisions within the working group, each one-on-one, and all of them completely technical with no non-technical questions. They also provided lunch with entry-level employees from working group. Was given the impression that would receive a follow-up contact within a few days but did not receive any contact until I inquired over a month later. Overall, the people were friendly and the campus was nice. Got the feeling that people enjoyed working there.
- What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc. Answer Question