AMD
3.1 of 5 1,091 reviews
www.amd.com Sunnyvale, CA 5000+ Employees

AMD Interview Questions & Reviews

Updated Jul 8, 2014
All Interviews Received Offers

Getting the Interview 

43%
21%
14%

Interview Experience 

66%
27%
6%

Interview Difficulty 

Average Difficulty
248 candidate interviews
Relevance Date Difficulty
in

Accepted Offer

Positive Experience

Average Interview

Senior Program Manager Interview

Senior Program Manager
Austin, TX

I applied online and the process took 6+ weeks - interviewed at AMD.

Interview Details – The recruiter was an outside contractor. All my interactions were professional and friendly. I was brought in for a second round of interviews to meet the Sr. Director and Director, which helped to increase my interest in the company overall. At the time, AMD was benefitting from a new product that was competitive to (exceeded in many ways) Intel's offering. AMD had also just landed a big customer that I worked for. Although, I found and applied for the position on my own online, AMD was very careful to ensure they were not poaching. Given this, my process took a bit longer. It was difficult to get an offer because AMD needed me to write a letter that showed my interest in them and my managers acknowledge (which I was not comfortable with) before they'd make me an offer. We eventually worked out the details and I was made an offer.

Interview Question – I don't remember. The interview process was very standard and not tricky or difficult. Possibly due to my level and the uniqueness of the role.   Answer Question

Negotiation Details – It was an aggressive offer - 30% pay increase from where I was. However, the base was intended to compensate me for my salary and bonus at my current position.

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Accepted Offer

Neutral Experience

Average Interview

Senior Software Development Engineer Interview

Senior Software Development Engineer
Sunnyvale, CA

I applied through an employee referral and the process took 4+ weeks - interviewed at AMD in October 2013.

Interview Details – There was one round phone interview before I got onsite interview invitation. In total, there were 6 rounds interview on campus, including last interview with the hiring manager and lunch interview. They are very friendly and professional.

Interview Question – All question are usual.   Answer Question

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Accepted Offer

Neutral Experience

Easy Interview

Co-Op Engineer Interview

Co-Op Engineer
Austin, TX

I applied online and the process took 5 days - interviewed at AMD in August 2013.

Interview Details – Connected through linkedIn and they were exactly looking for my kind of experience in computer architecture and programming. I had a telephonic conversation and a meeting after that with only questions if I was interested in the position. Nothing technical as such just got to know about my skill set.

Interview Question – I did not get any difficult questions.   Answer Question

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Accepted Offer

Positive Experience

Easy Interview

Engineer Co-Op Interview

Engineer Co-Op

I applied through a recruiter and the process took 3 weeks - interviewed at AMD.

Interview Details – Met recruiter (my future manager) at a career fair, spoke to him for a bit and gave him my resume. Got a call a few weeks later from someone on his team for a quick phone interview, which lasted about 15 minutes. Received an offer about a week later.

Interview Question – Asked me to talk about my work in student organizations I had listed on my resume, as well as my time management techniques.   View Answer

Negotiation Details – Pay is based off of your standing in school and is non-negotiable.

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No Offer

Neutral Experience

Average Interview

Hardware Engineer Interview

Hardware Engineer

I applied online and the process took 1 week - interviewed at AMD in September 2013.

Interview Details – Phone interview

Interview Question – The differences between Verilog simulator and C++ simulator   Answer Question

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No Offer

Positive Experience

Average Interview

Entry Level Hardware Engineer Interview

Entry Level Hardware Engineer
Austin, TX

I applied online and the process took 6 days - interviewed at AMD in August 2013.

Interview Details – I applied the job via company website and got the chance to be phone interviewed the same day I applied...... I was in a vacation at that time!!!! Anyway, we set up a time and did an hour interview four days later.... The questions covers all the stuffs from hardware to software. They are not difficult individually, however, it requires you know every aspect of the computer. My answers to those questions are ..... not bad, according to the recruiter. But I do fail some of them. Finally, I cannot get the chance to do a onsite interview. I lose a good opportunity!!!!

Interview Question – The process of changing page when there is a page fault. Very detail!   Answer Question

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No Offer

Neutral Experience

Average Interview

Physical Design Engineer Interview

Physical Design Engineer

Interviewed at AMD

Interview Details – Phone interview: First described what this team does and what this position for. Then asked some questions on my resume, about my educations and experience. He let me choose one of favorite project and describe to him. Then asked a question, which can be considered as several sub questions.

Interview Question – While synthesizing memory(SRAM), how to estimate the area, delay and power? What can you do to solve time violation.   Answer Question

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Declined Offer

Positive Experience

Average Interview

Processor Design Engineer Interview

Processor Design Engineer
Austin, TX

I applied online and the process took 4+ weeks - interviewed at AMD in September 2013.

Interview Details – I got email for phone interview.
In the interview they told me about the project and then there were some technical questions.
Questions were basic and were expected.
1. Difference between cache consistency and cache coherency
2. What is setup and hold time
3. What is Virtual functions
4. What is generic programming
5. What is difference between virtual functions and generic programming
6. Questions about how simulators work
7. A question which was on calculating FIFO buffer length

Reason for Declining – I got better offer from other company

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Accepted Offer

Positive Experience

Average Interview

Senior Engineer Interview

Senior Engineer
Austin, TX

I applied through a staffing agency and the process took 2 months - interviewed at AMD in April 2011.

Interview Details – Hired through contracting company Volt. Spoke to Hiring Manager at AMD and received a call 1 week later that I had gotten the Job.

Interview Question – No question was difficult or unexpected. I did a lot of studying about this company before the interview.   Answer Question

Negotiation Details – I was able to negotiate Per Diem since I lived in another city. This is critical when having to relocate for a new job.

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7 people found this helpful

No Offer

Positive Experience

Difficult Interview

Graduate Design Engineer/Physical Design Interview

Graduate Design Engineer/Physical Design
Austin, TX

I applied through an employee referral and the process took 2+ weeks - interviewed at AMD in May 2013.

Interview Details – I got the call for telephonic interview through referral. Phone interview was around 45 - 60 min. After the getting through the phone screen, was invited for onsite.

The onsite was from 9am - 4pm, with 6 1:1 45min sessions and lunch with the manager.

Interview Question – Phone Screen:
>Difference b/w latch and flip flop
>Clock domain crossing; synchronizers, how they are placed wrt floor planning
>Explain what is IR drop and EM and ways to reduce it
>Inverter sizing; wrt mobility, drive strengths, matching charge/ discharge delays, rise/ fall times
>Verilog blocking and non-blocking statements and what do they realise in hw
>Dynamic power dissipation and ways to reduce it
>Static power dissipation and ways to reduce it; RBB/ FBB, multiple Vt devices
>A buffer ckt, wherein the o/p of inv1, voltage is equal to the switching threshold of inv2, now what is the o/p of the buffer; static power dissipation, dc path question
>Realise AND/OR/NAND logic using 2:1 mux
>What is setup/ hold time violations; meta-stability issues
>How to overcome setup/ hold time violations
> crosstalk and how will you reduce it

Onsite:
Round #1:
>Nmos pull up, Pmos pull down structure with rising step input. Was asked to draw the output pattern and explain the functioning of the circuit and also to predict what it's used as.
>asked to draw transistor level diag of 2 i/p nand gate and explain how i size it
>was given a logical path and i had to size the devices using logical effort
>asked to draw a transistor level diag of flip flop and point out the setup and hold nodes
>2 i/p dynamic nand gate -> cascade of 2 stages connected directly w/o a domino inv; asked to draw the wave patter at final out
>contd: now with domino inv; asked how big it should be
>contd: level restorer; concepts of full keeper, whether it can be used in the given case
>concepts of clock feed through, charge sharing, back gate coupling

Round #2:
>questions from my resume regarding the projects that i have worked on and also some of asic tools related to PD
>how do you compare two values; what logic you will use
>timing optimization wrt given logic structure; had to re-arrange the logic blocks and also make use of alternate gates to implement the logic and meet the timing considerations
>explain crosstalk; what is aggressor and victim, how will you reduce it
>some questions on clock tree synthesis; was given a scenario with inv's of specific drive strengths and asked to place them accordingly on the given grid
>given a <63:0> 2 i/p and gate, where will you position the gate in a rectangle block taking into consideration crosstalk; floor planning wrt crosstalk issues
>asked about async fifo (from resume); corner cases and working

ROund #3:
>asked to implement a boolean logic using k-map minimization
>pseudo code explaining blocking and non-blocking usage, taking example of flip flop
>cache - write back, write through caches, cache replacement policies, messi protocol, cache organization - direct mapped, set associative
>specific questions from my resume

Round #4:
>setup/ hold time violations
>given scenario: if receiving flop is delayed wrt launching flop, what timing parameter is violated and how to rectify it
>contd: if launching flop is delayed wrt receiving flop, again what is affected and how to overcome the issue
>wrt my resume (PLL design), few questions regarding charge pump design

Round #5:
>signal integrity issues - cross talk, IR drop, EM with specific scenarios and ways to reduce
>2 i/p nor gate with sizing and its layout; multi fingering
>ways to reduce interconnect delay
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