Work in HR? Unlock Free Profile

AMD Interview Questions & Reviews

Updated Jul 20, 2014
All Interviews Received Offers

Getting an Interview  


Interview Experience  


Interview Difficulty  

Average Difficulty
250 candidate interviews
Relevance Date Difficulty
7 people found this helpful

No Offer

Positive Experience

Difficult Interview

Graduate Design Engineer/Physical Design Interview

Graduate Design Engineer/Physical Design
Austin, TX

I applied through an employee referral and the process took 2+ weeks - interviewed at AMD in May 2013.

Interview Details – I got the call for telephonic interview through referral. Phone interview was around 45 - 60 min. After the getting through the phone screen, was invited for onsite.

The onsite was from 9am - 4pm, with 6 1:1 45min sessions and lunch with the manager.

Interview Question – Phone Screen:
>Difference b/w latch and flip flop
>Clock domain crossing; synchronizers, how they are placed wrt floor planning
>Explain what is IR drop and EM and ways to reduce it
>Inverter sizing; wrt mobility, drive strengths, matching charge/ discharge delays, rise/ fall times
>Verilog blocking and non-blocking statements and what do they realise in hw
>Dynamic power dissipation and ways to reduce it
>Static power dissipation and ways to reduce it; RBB/ FBB, multiple Vt devices
>A buffer ckt, wherein the o/p of inv1, voltage is equal to the switching threshold of inv2, now what is the o/p of the buffer; static power dissipation, dc path question
>Realise AND/OR/NAND logic using 2:1 mux
>What is setup/ hold time violations; meta-stability issues
>How to overcome setup/ hold time violations
> crosstalk and how will you reduce it

Round #1:
>Nmos pull up, Pmos pull down structure with rising step input. Was asked to draw the output pattern and explain the functioning of the circuit and also to predict what it's used as.
>asked to draw transistor level diag of 2 i/p nand gate and explain how i size it
>was given a logical path and i had to size the devices using logical effort
>asked to draw a transistor level diag of flip flop and point out the setup and hold nodes
>2 i/p dynamic nand gate -> cascade of 2 stages connected directly w/o a domino inv; asked to draw the wave patter at final out
>contd: now with domino inv; asked how big it should be
>contd: level restorer; concepts of full keeper, whether it can be used in the given case
>concepts of clock feed through, charge sharing, back gate coupling

Round #2:
>questions from my resume regarding the projects that i have worked on and also some of asic tools related to PD
>how do you compare two values; what logic you will use
>timing optimization wrt given logic structure; had to re-arrange the logic blocks and also make use of alternate gates to implement the logic and meet the timing considerations
>explain crosstalk; what is aggressor and victim, how will you reduce it
>some questions on clock tree synthesis; was given a scenario with inv's of specific drive strengths and asked to place them accordingly on the given grid
>given a <63:0> 2 i/p and gate, where will you position the gate in a rectangle block taking into consideration crosstalk; floor planning wrt crosstalk issues
>asked about async fifo (from resume); corner cases and working

ROund #3:
>asked to implement a boolean logic using k-map minimization
>pseudo code explaining blocking and non-blocking usage, taking example of flip flop
>cache - write back, write through caches, cache replacement policies, messi protocol, cache organization - direct mapped, set associative
>specific questions from my resume

Round #4:
>setup/ hold time violations
>given scenario: if receiving flop is delayed wrt launching flop, what timing parameter is violated and how to rectify it
>contd: if launching flop is delayed wrt receiving flop, again what is affected and how to overcome the issue
>wrt my resume (PLL design), few questions regarding charge pump design

Round #5:
>signal integrity issues - cross talk, IR drop, EM with specific scenarios and ways to reduce
>2 i/p nor gate with sizing and its layout; multi fingering
>ways to reduce interconnect delay
  Answer Question

Accepted Offer

Neutral Experience

Difficult Interview

Senior Manager Interview

Senior Manager

I applied through other source and the process took 5 days - interviewed at AMD.

Interview Details – very technical interview

Interview Question – Be ready to handle questions from college text books on engineering   Answer Question

Negotiation Details – the offer at the time was very good. I did not negotiate

No Offer

Neutral Experience

Average Interview

SOC Atchietec Interview

SOC Atchietec

I applied online - interviewed at AMD in August 2013.

Interview Details – phone interview, asked about C++ programming and concept of computer architecture.
1. write c code to check prime number
2. write c code to detect different elements in two array
3. verilog blocking and non-blocking
4. different b/w c and verilog
5. different b/w template and virtual funciton
6. what is cache, cache coherence
7. different b/w stack and heap
8. what is interrupt

Interview Question – difference bw template and virtual function   Answer Question

We want your feedback – Is this interview information helpful to you?  Yes | No

Accepted Offer

Neutral Experience

Average Interview

Design Engineer II Interview

Design Engineer II
Austin, TX

I applied online and the process took 1+ week - interviewed at AMD in June 2013.

Interview Details – Very good. Manager is very nice

Interview Question – not meet. everything went well   Answer Question

Accepted Offer

Positive Experience

Difficult Interview

Director Interview

Austin, TX

I applied through a recruiter and the process took 2 weeks - interviewed at AMD in November 2009.

Interview Details – The interview process started out with a couple of telephone interviews. The interviews focused on skills, knowledge, and similar normal interview questions. The people I talked to spent a lot of time talking about the organization they wanted me to join and the challenges they were facing, and they were very upfront.

Interview Question – Spent about 15 minutes getting into the specifics of how I would fix a very particular problem they were facing, and they had some ideas already for what they expected for an answer.   Answer Question

No Offer

Neutral Experience

Software Engineer Interview

Software Engineer

I applied online and interviewed at AMD.

Interview Details – by phone

Interview Question – Hex bit operation   Answer Question

Accepted Offer

Neutral Experience

Design Engineer II Interview

Design Engineer II

Interviewed at AMD

Interview Details – Got a phone screen talking about background and projects did at school. The next week went to onsite on Sunnyvale. A nice place.
Meet with 7 team member in that team. each about an hour. Different member have checked differnet area of ASIC design and verification aspects/
Overall, a nice experience.

Interview Question – How to input test signals to test chip after frabrication.   Answer Question

Declined Offer

Positive Experience

Average Interview

Project Manager/Business Analyst Interview

Project Manager/Business Analyst
Austin, TX

I applied online and the process took 3 weeks - interviewed at AMD in April 2013.

Interview Details – Phone: Initial screening call with HR rep (salary not discussed)
Phone: Hiring Manager Phone Interview (salary not discussed)
Face2Face: On-site Interview (salary not discussed)
Phone: Offer made by HR rep via phone (salary preferences, HR's pay range for the position, and start date discussed; no other benefits discussed at this time)
Phone: HR called to state that position was being reclassified to a much lower pay scale; they also stated they liked me but were sure that I wouldn't be interested in the much lower pay

Interview Question – Tell me why I shouldn't hire you for this job.   Answer Question

Reason for Declining – Salary package had not been agreed upon when HR notified me that, due to internal challenges, the position was changed to a much lower pay level.

Accepted Offer

Positive Experience

Senior Product Development Engineer Interview

Senior Product Development Engineer
Austin, TX

I applied through an employee referral and the process took a day - interviewed at AMD.

Interview Details – Six interviews with Senior, Member of Technical Staff and Manager. Last one day

Interview Question – In general they check you general knowledge on EE   Answer Question

Negotiation Details – None

Accepted Offer

Positive Experience

Difficult Interview

Software Engineer/Contractor Interview

Software Engineer/Contractor
Austin, TX

I interviewed at AMD in April 2012.

Interview Details – Team architect called based on provided resume/experience. He provided clarity and specific details of overview of development environment and details regarding interview process. He just checked to confirm some details over resume and invited for Onsite Interview. Half day of very technical onsite interview with team and hiring mgrs.

Interview Question – Describe the most technical project you've done on whiteboard.   Answer Question

See What AMD Employees Are Saying

 Former Senior Administrative Assistant in Fort Collins, CO

Pros: “Good immediate management. Fairly open in decision making processes and good benefits.” Full Review

Worked for AMD? Contribute to the Community!

The difficulty rating is the average interview difficulty rating across all interview candidates.

The interview experience is the percentage of all interview candidates that said their interview experience was positive, neutral, or negative.

Your response will be removed from the review – this cannot be undone.