The process took a day - interviewed at Actel in April 2009.
The initial phone interview was with 2 or 3 engineers. They asked basic questions such as logic, setup/hold times, transistor basics. They also asked for scripting/software background.
The on-site one was much more expansive. It spanned over 5 hours with 7 different people and was very technical, albeit not too hard. I was asked to draw out characteristic curves, explain parts of the curve, solve some basic logic problems on paper. Also I was shown some verilog code and I had to be able to tell what it was. I was asked to describe how to make an FSM, how a PLL works, etc., all verbal answers.
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