Glassdoor is your free inside look at Ambarella interview questions and advice. All 16 interview reviews posted anonymously by Ambarella employees and interview candidates.
Ambarella Interview Questions & Reviews
Getting the Interview 16 Interviews
Interview Experience 9 Ratings
Summer Intern-Summer Intern at Ambarella
No Offer – Interviewed in Santa Clara, CA Feb 2013 – Reviewed May 7, 2013 New
Interview Details – Submitted resume at the career fair, and then get e-mails to have phone interview. Three rounds of phone interviews.
Interview Question –
1. Basic circuit design and logic design question
2. Basic verilog question (e.g. verilog module to swap 2 variables, 4-to-1 mux etc.)
3. Write a verilog testbench module which generates 2 output signals:
1) clock - at 1GHZ
2) reset - asserted (1) for first 100 cycles and then deasserted (0)
4. 8 entry FIFO module
5. What are the 2 components of a chip power and how will you reduce each one?
Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
ASIC Design Engineer Intern at Ambarella
No Offer – Reviewed Mar 2, 2013
Interview Details – Submit resume during the career fair, and then get e-mails to have interview. Three rounds of phone interviews
Interview Question –
Detect the leading one in a sequence.
Find the second smallest number in an array.
Determine whether a infinite sequence is the multiple of 5.
Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
VLSI Design at Ambarella
No Offer – Interviewed in Feb 2013 – Reviewed Feb 25, 2013
Interview Details – Summit my application through career fair. 45mins Phone Interview. The interviewer talked about the company and asked my questions for 10mins. Question on FSM design of sequencial detector, such as 100011, and Verilog coding. How to find the second largest number in an array in C. Asked question on my project.
Interview Question – C language programmng Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Summer Intern at Ambarella
No Offer – Reviewed Feb 25, 2013
Interview Details – On campus career fair submitted resume, phone interview. Totally technical, questions on clock skew/jitter, string detector, verilog data width and implementing gate with MUX
Interview Question – Compare the advantage of shift register and FSM in implementing string detector Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Analog Design Engineer at Ambarella
No Offer – Interviewed in Santa Clara, CA – Reviewed Feb 23, 2013
Interview Details –
The Interviewer just asked about the project in your resume:
the company need someone who can use verilog, and understand the layout of your design.
No hiring entry-level engineer
Helpful Interview?
Yes |
No
Problem with this interview?
ASIC Design Engineer at Ambarella
No Offer – Interviewed in Santa Clara, CA Jan 2013 – Reviewed Jan 31, 2013
Interview Details –
Initially applied online and got email for interview. They seems to tend to interview local candidates so I am told to drop by their office directly. It is an 1-hour interview with several questions which include state machine, sorting, and testing. ASIC design is really different from Analog. Huge programming skills are required.
Nice people there.
Interview Question –
1. sequence detector
2. get second largest number of a unsorted array
3. setup and hold time
4. some testing questions.
Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Analog Design Engineer at Ambarella
No Offer – Interviewed in Santa Clara, CA Nov 2012 – Reviewed Jan 3, 2013
Interview Details – I got a phone interview and after less than a week I was told to arrange an on-site interview. Almost all interview questions are technical but basic. Familiarity to the topics and speed of response to those questions may be critical.Though the questions are not easy, the people interview me are quite kind.
Interview Question –
1. What are DNL and INL of an ADC? What's the difference?
2. What's quantization noise? Derive signal-to-quantization-noise ration.
3. How to compensate an OPAMP?
4. When the size of tail current transistor increase, how will it affect the phase noise of a VCO?
Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Logic Designer at Ambarella
No Offer – Interviewed in San Jose, CA May 2012 – Reviewed Jun 2, 2012
Interview Details – I met and talked with one of the VP on a campus recruiting event. The hiring process was described as consisting of an 1-hour phone screen interview and an 5-hour on-site interview by 5 interviewers. Everything should be very technical. The phone interview I had was almost purely technical with no chit-chat, with just a brief introduction then actually 30 minutes of problem solving. Need to be able to design logic gate circuits, both combinational and sequential. Need to know logic, diagrams, and coding. The company culture seems serious and fast-pace.
Interview Question – Design a single-bit-input, single-bit-output machine that outputs 1 when it recognizes the pattern 10110 and output 0 at all other times. View Answer
Helpful Interview?
Yes |
No
Problem with this interview?
Engineering at Ambarella
No Offer – Interviewed in Santa Clara, CA May 2012 – Reviewed May 26, 2012
Interview Details – Ask me questions on my resume. Ask data structures and wrote a easy algorithm. and some architecture questions.
Interview Questions
- What is virtual memory? Answer Question
- Different between FF and Latch Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
Verification Engineer at Ambarella
No Offer – Interviewed in Santa Clara, CA May 2010 – Reviewed Sep 22, 2010
Interview Details – Phone Interview followed by onsite interview. Did not pay for travelling expense.
Interview Question – Given a black box and input/output ports and functionality, translate from C to verilog a block of code. Answer Question
Helpful Interview?
Yes |
No
Problem with this interview?
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