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Interview Question for Graduate Technical Intern at Intel Corporation:

Oct 9, 2011

Can you build a BRAM with one read port and one write port? Two read ports and one write port? Two read ports and two write ports? How would you expand the data width of the memory given that you only have 8-bit wide BRAMs available on the FPGA?

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Oct 9, 2011

by Interview Candidate:

For data width, I mentioned banking of BRAM, with separate series of addresses exclusive to each bank.

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Microprocessor, Microcontroller & Digital Signal Processor Manufacturing

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Interview Question for Graduate Technical Intern at Intel Corporation:

Can you build a BRAM with one read port and one write port? Two read ports and one write port? Two read ports and two write ports? How would you expand the data width of the memory given that you only have 8-bit wide BRAMs available on the FPGA?

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