View All num of num Add Photos Einfochips This employer has taken extra steps to respond to reviews and provide job seekers with accurate company information, photos, and reviews. Interested for your company?Learn More. www.einfochips.com Employer Engaged Overview Reviews Salaries Interviews Jobs Photos Benefits 85 Reviews 103 Salaries 19 Interviews Follow Add Review or Salary Follow Add Review or Salary Interview Question Assistant ASIC Engineer Interview(Student Candidate) Ahmedabad (India) Einfochips Differentiate between = and => sings in verilog. Tags: See more , See less 8 Answer Add Tags Answer Interview Answer 2 Answers ▲ 0 ▼ As far as I remember,first is simultaneous assignment and the other is sequential. In reality, every flip flop is made of = inside, => sign is just to simulate sequential code to carry out verification. Interview Candidate on Nov 16, 2011 ▲ 1 ▼ = is blocking statemnt whereas <= is non blocking statemnt..so basically dealing = solves serially nd <= solves paralley. zeal ghia on Aug 28, 2012 Add Answers or Comments To comment on this, Sign In or Sign Up.