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Einfochips Assistant ASIC Engineer Interview Question (student candidate)

I interviewed in Ahmedabad (India) and was asked:
"Differentiate between = and => sings in verilog."
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Part of a Assistant ASIC Engineer Interview Review - one of 16 Einfochips Interview Reviews

Answers & Comments

of 0

As far as I remember,first is simultaneous assignment and the other is sequential. In reality, every flip flop is made of = inside, => sign is just to simulate sequential code to carry out verification.

- Interview Candidate on Nov 16, 2011
of 1

= is blocking statemnt whereas <= is non blocking statemnt..
so basically dealing = solves serially nd <= solves paralley.

- zeal ghia on Aug 28, 2012

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