Dolphin Technology Inc
Getting an Interview
Getting an Interview
Interviews for Top Jobs at Dolphin Technology Inc
- Circuit Design Engineer (6)
- Applications Engineer (1)
- Helpdesk Support (1)
- Electrical Engineer (1)
- Digital Circuit Design Engineer (1)
- Digital Design Engineer (1)
- Engineering (1)
- Validation Engineer (1)
- Verification Engineer (1)
- Circuit Design/Analog Mixed Signal Design (Multiple Positions Available) (1)
- High Speed I/O (1)
- Circuit Design Engineer(SRAM Memory Or High Speed IO) (1)
- Circuit Design Engineer (New Grad) (1)
- SRAM Designer (1)
- Digital Circuit Design Engineer - SRAM & Memory Or High Speed IO & Standard Cells (1)
- Circuit Design (1)
- Application Details
I applied online – interviewed at Dolphin Technology Inc in November 2014.Interview Details
I submitted application and got on-site interview directly, then they arranged my interview on one afternoon, but they don't cover the travel expense, so I booked the flight by myself. One day before the interview, they emailed me and informed me the position is taken, so my interview is canceled, although I already arrived at San Jose at that time for interview. They don't care my cost on flight ticket at all so that I lost $500, two days and an interview opportunity. I don't what to say about it, if you decide to choose one candidate among applicants, you should at least interview all the applicants that got interview opportunity. It concerns with the reputation of the company!No OfferNegative Experience
- Interview Details
They gave me an email and told me to be onsite directly. 3 people talked with me and they were focusing on different area. Just had a chat with each of them and the questions they ask were easy. Most of the questions were focusing on resume.Interview Questions
No OfferEasy Interview
- Just basic questions. Answer Question
- Application Details
I applied online. The process took 2 weeks – interviewed at Dolphin Technology Inc in October 2014.Interview Details
I applied online and a few days later I got an email inviting me for an onsite interview. Strangely they skipped the phone interview and I though it's because my resume was looking good enough to them but I was wrong! As it turned out later they even hadn't looked at my resume. I wasn't living in San Jose and the email clearly stated that they won't reimburse travel expenses. At the beginning I was hesitant to spend a lot of money to book a flight and hotel to go to onsite interview but later I thought it might be worth it if I get the job.
The interview was on Friday afternoon. There was no schedule or plan of any sort for who should interview me and when. The HR just selected two junior engineers on the spot to interview me. It was obvious that they were not prepared to interview me and they had no idea what is in my resume. Then a senior engineer showed up to interview me. The moment he looked at my resume he told me that I don't seem a good fit to the job and that they are looking for someone with more transistor-level design experience and less RTL design experience. I liked his quick and honest feedback but I also got very annoyed that why they didn't check my resume beforehand so I didn't have to spend significant time and money to prepare and travel to San Jose. The senior engineer who seemed a nice guy then gave me some advice on choosing the right career path that I really liked and appreciated but still it didn't make me less upset for wasting my time and money to go to a useless interview.
I just wrote this to let you know that if you got direct onsite interview first of all do not get excited and then if you are not living in San Jose you might want to think twice before spending a lot of money to plan a trip.Interview Questions
No OfferNegative ExperienceEasy Interview
- All general and easy questions on the MOSFET and inverter operation, transistor-level gate design (e.g. static and dynamic XOR), how SRAM and Sense Amplifier work etc. Answer Question
2 people found this helpfulApplication Details
I applied online. The process took 2 days – interviewed at Dolphin Technology Inc.Interview Details
Got Direct Onsite Interview call. The interview was scheduled on Friday in the later half of the day. 3 rounds took place of around 45 minutes each. Was called for another 3+1(Meeting with Director) rounds on Monday as people left early because of being a Friday. First 3 rounds were taken by 1-2 years experienced people. Last 3 rounds by senior Engineers who asked really good questions.
Here are the questions asked. People should not panic looking at some questions as most of them were from the projects:
1) What is Flat Placement?
2) Sense Amplifier Working and Schematic
3) How BL got a glitch during read? Ans: Sense Amp’s NMOS driven by BL and BLB with 0.9V and 0.1V gives 2 discharge paths.(Draw yourself and see)
4) Out of NMOS logic on NAND(series NMOS), NOR(Parallel NMOS) and inverter(Single NMOS), which is faster? Which consumes maximum power.
5) Which part of SRAM design consumes the most power? Ans: Read. Bitlines charging and discharging consumes a lot of power and is the reason to cutoff Sense Amp after 100mV to not let bit line drain all down to 0.
6) Pass Transistor circuit voltages at some nodes.
7) Negative Setup and Hold. Can we have both occurring together?
8) Verilog always block with blocking and nonblocking DFF implementation and what hardware they will synthesize by both?
9) Monte-Carlo simulation of 100mV sense Amp differential voltage at worst and best case.
10) What is a Ring Oscillator and what are its applications?
11) What is worst P(Process)?
12) Simulated Annealing Algorithm? What other Algorithm for Placement?
13) SRAM Layout
14) Latch Setup Hold and why don’t we have setup and hold of latch at positive edge?
15) Tristate implementations and which one is better? consider in terms of power
16) SRAM Read waveforms
17) (A+B)C + D implementation and sizing with the inverter sized to 1 and 2 for NMOS and PMOS respectively.
18) What is STA?
19) How you measured the Wirelength in Flat Placement?
20) How you decide the 80mV value for Read Sense Amp?
21) How you assert SAE to get this value?
22) How can you cut off your BL and BLB after sense AMP has read the value to save power.
From Senior People:
23) Draw layout of SRAM cell
24) How you size it?
25) How you determine Read and Write SNM.
26) Draw Sense Amplifier schematic that you used. How you assert SA enable signal? How do you determine delta V for SenseAmp?
27) Draw Transistor characteristics and why it is quadratic over the top at saturation? Could it be something else?(He wanted to know the short channel equation)
28) What you did in the ring oscillator project and what were the maximum and minimum operating frequencies?
29) Why pinch off occurs?
30) Find how many times your name occurs in a text file (PERL)
31) Write verilog always block for a DFF and a Dlatch
32) Draw NAND schematic and size it for FO4
33) Do you have any other offer or interview?Interview QuestionsNegotiation DetailsCouldn't negotiate as I am a Fresher.Accepted OfferPositive ExperienceAverage Interview
3 people found this helpfulApplication Details
I applied online – interviewed at Dolphin Technology Inc.Interview Details
Applied online and phone interview was scheduled based on vacancy.
Phone interview questions:
latch v/s FF
blocking/ non blocking
setup n hold
sizing of sram for read and write
inverter sizing, 2 ip nand sizing
why pmos is sized up compared to nmos in an inverter
miller cap effect in inverter
if ip to inverter is 0.5 VDD, what is op value
inverter with a series nmos, what happens and
with inc in temp how a fet behavesInterview Questions
No OfferPositive ExperienceAverage Interview
- everything was conceptual Answer Question
- Application Details
I applied online – interviewed at Dolphin Technology Inc in April 2013.Interview Details
applied on line and They skipped the phone interview.
got a phone call from HR and had an on site interview in the next week. The process was very fast, I got declined after two daysInterview Questions
No OfferAverage Interview
- 1. given a simple logic, inputs, logic delay. draw the timing diagram for the circuit Answer Question
- 2. inverter operation region, pmos, nmos state Answer Question
- 3. design a state machine to detect "110101" Answer Question
- Size of SRAM for 6T SRAM, why? (what is read disturbance ), advantage of 8T SRAM.
Transistor sizing for CMOS logic Answer Question
- power consumption formula , dynamic, switching, leakage. How to improve power consumption based on three different components Answer Question
5 people found this helpfulApplication Details
I applied online. The process took 3 days – interviewed at Dolphin Technology Inc in March 2013.Interview Details
Resume Submitted online - got an email regarding phone interview
Phone interview - straight to the business started asking technical Questions
1. Explain CMOS operation regions
2. Sizing of 2 input NAND Gate
3. difference between blocking and Non-blocking(Verilog)
4. What are arrays and Hashes in PERL
Selected for On-site with 1:1 round with 7 Engineers
1. He drew digital circuits with basic Gates and the delays and asked to draw waveforms
2. C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question)
3 & 4. Asked on my Resume and Research work
5. Asked me more in detail about CMOS like why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc
6. Director discussed more about the company
7. Asked about Flip Flops and setup hold time and Max Frequency of a sequential and Combinational circuitInterview Questions
Negotiation DetailsNo Negotiation as I am a Fresh GradAccepted OfferPositive ExperienceDifficult Interview
- He drew digital circuits with basic Gates and the delays and asked to draw waveforms Answer Question
- why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc View Answer
- C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question) View Answer
- Flip Flops and setup hold time and Max Frequency of a sequential and Combinational circuit Answer Question
2 people found this helpfulApplication Details
I applied online. The process took 5 days – interviewed at Dolphin Technology Inc in March 2013.Interview Details
The whole process is it: I received the call from the company after I submit the resume. They schedule the on-site interview directly. They comes with different people from different group. First person ask about inverter and then NAND gate, and how to size them to make rise time and fall time equally. Then ask about the verilog question. Second person draw a pics with four different circuit about the circuit and asked when the clock comes in what the output will be. And then ask about the passgate flip-flop. The third one asked C programming and he gave me a test sheet to write up.No OfferNeutral ExperienceAverage Interview
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