Dolphin Technology Inc
2.5 of 5 2 reviews
www.dolphin-ic.com San Jose, CA 50 to 149 Employees

Dolphin Technology Inc Interview Questions & Reviews

Updated Jun 17, 2014
All Interviews Received Offers

Getting the Interview 

88%
3%
3%

Interview Experience 

38%
53%
7%

Interview Difficulty 

Average Difficulty
18 candidate interviews
Relevance Date Difficulty

Accepted Offer

Positive Experience

Average Interview

Digital Circuit Design Engineer - SRAM & Memory Or High Speed IO & Standard Cells Interview

Digital Circuit Design Engineer - SRAM & Memory Or High Speed IO & Standard Cells
San Jose, CA

I applied online and the process took 2 days - interviewed at Dolphin Technology Inc.

Interview Details – Got Direct Onsite Interview call. The interview was scheduled on Friday in the later half of the day. 3 rounds took place of around 45 minutes each. Was called for another 3+1(Meeting with Director) rounds on Monday as people left early because of being a Friday. First 3 rounds were taken by 1-2 years experienced people. Last 3 rounds by senior Engineers who asked really good questions.
Here are the questions asked. People should not panic looking at some questions as most of them were from the projects:

1) What is Flat Placement?
2) Sense Amplifier Working and Schematic
3) How BL got a glitch during read? Ans: Sense Amp’s NMOS driven by BL and BLB with 0.9V and 0.1V gives 2 discharge paths.(Draw yourself and see)
4) Out of NMOS logic on NAND(series NMOS), NOR(Parallel NMOS) and inverter(Single NMOS), which is faster? Which consumes maximum power.
5) Which part of SRAM design consumes the most power? Ans: Read. Bitlines charging and discharging consumes a lot of power and is the reason to cutoff Sense Amp after 100mV to not let bit line drain all down to 0.
6) Pass Transistor circuit voltages at some nodes.
7) Negative Setup and Hold. Can we have both occurring together?
8) Verilog always block with blocking and nonblocking DFF implementation and what hardware they will synthesize by both?
9) Monte-Carlo simulation of 100mV sense Amp differential voltage at worst and best case.
10) What is a Ring Oscillator and what are its applications?
11) What is worst P(Process)?
12) Simulated Annealing Algorithm? What other Algorithm for Placement?
13) SRAM Layout
14) Latch Setup Hold and why don’t we have setup and hold of latch at positive edge?
15) Tristate implementations and which one is better? consider in terms of power
16) SRAM Read waveforms
17) (A+B)C + D implementation and sizing with the inverter sized to 1 and 2 for NMOS and PMOS respectively.
18) What is STA?
19) How you measured the Wirelength in Flat Placement?
20) How you decide the 80mV value for Read Sense Amp?
21) How you assert SAE to get this value?
22) How can you cut off your BL and BLB after sense AMP has read the value to save power.

From Senior People:
23) Draw layout of SRAM cell
24) How you size it?
25) How you determine Read and Write SNM.
26) Draw Sense Amplifier schematic that you used. How you assert SA enable signal? How do you determine delta V for SenseAmp?
27) Draw Transistor characteristics and why it is quadratic over the top at saturation? Could it be something else?(He wanted to know the short channel equation)
28) What you did in the ring oscillator project and what were the maximum and minimum operating frequencies?
29) Why pinch off occurs?
30) Find how many times your name occurs in a text file (PERL)
31) Write verilog always block for a DFF and a Dlatch
32) Draw NAND schematic and size it for FO4
33) Do you have any other offer or interview?

Interview Questions

  • Why there is a pinch-off during saturation mode of a CMOS device?   View Answer
  • How Sense Amplifier works.   View Answer

Negotiation Details – Couldn't negotiate as I am a Fresher.

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No Offer

Neutral Experience

Average Interview

SRAM Designer Interview

SRAM Designer

I applied online - interviewed at Dolphin Technology Inc in April 2013.

Interview Details – applied on line and They skipped the phone interview.
got a phone call from HR and had an on site interview in the next week. The process was very fast, I got declined after two days

Interview Questions

  • 1. given a simple logic, inputs, logic delay. draw the timing diagram for the circuit   Answer Question
  • 2. inverter operation region, pmos, nmos state   Answer Question
  • 3. design a state machine to detect "110101"   Answer Question
  • Size of SRAM for 6T SRAM, why? (what is read disturbance ), advantage of 8T SRAM.
    Transistor sizing for CMOS logic
      Answer Question
  • power consumption formula , dynamic, switching, leakage. How to improve power consumption based on three different components   Answer Question

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No Offer

Neutral Experience

Circuit Design Engineer Interview

Circuit Design Engineer

Interviewed at Dolphin Technology Inc

Interview Details – the onsite interview took 7 round, each interview about 30 to 40 minutes

Interview Question – all basic questions   Answer Question

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No Offer

Neutral Experience

Circuit Design Interview

Circuit Design

Interviewed at Dolphin Technology Inc

Interview Details – On site interview 4 persons

Interview Question – SRAM stucture   Answer Question

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2 people found this helpful

No Offer

Negative Experience

Easy Interview

Validation Engineer Interview

Validation Engineer
San Jose, CA

I applied online and the process took a day - interviewed at Dolphin Technology Inc in July 2012.

Interview Details – Interviewed for a position of Junior level Validation engineer at their San Jose office.
Interviewers were fresh graduates with less than a year's experience and I was interviewing for a position that required 2 years experience.
The same interviewer got mad at me because I would need H1B sponsorship while my name in my resume had made him think I would not ! (BTW He himself was Indian and was on a H1!)
Interview was extremely un-organised and one of the interviewer got kind of offended because he could not understand my PERL program using Regular expressions.
After the first 2 rounds, they had me wait for around 25 mins for the next interviewer, who came in only after I asked the receptionist about it.
I was not too unhappy to have not heard back from them ..

Interview Question – Write a PERL script to find a certain key word in a text file.
Solid state electronics questions.
Questions about latches and flipflops
Basic VERILOG coding questions.
Basic C coding questions - (Write a function that accepts 3 numbers and returns the highest 2- this was one of the best questions in the interview, asked by a more experienced engineer)
  Answer Question

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3 people found this helpful

No Offer

Positive Experience

Average Interview

Circuit Design Engineer Interview

Circuit Design Engineer

I applied online and interviewed at Dolphin Technology Inc.

Interview Details – Applied online and phone interview was scheduled based on vacancy.

Phone interview questions:
latch v/s FF
blocking/ non blocking
setup n hold
sizing of sram for read and write
inverter sizing, 2 ip nand sizing
why pmos is sized up compared to nmos in an inverter
miller cap effect in inverter
if ip to inverter is 0.5 VDD, what is op value
inverter with a series nmos, what happens and
with inc in temp how a fet behaves

Interview Question – everything was conceptual   Answer Question

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5 people found this helpful

Accepted Offer

Positive Experience

Difficult Interview

Circuit Design Engineer(SRAM Memory Or High Speed IO) Interview

Circuit Design Engineer(SRAM Memory Or High Speed IO)
San Jose, CA

I applied online and the process took 3 days - interviewed at Dolphin Technology Inc in March 2013.

Interview Details – Resume Submitted online - got an email regarding phone interview
Phone interview - straight to the business started asking technical Questions
1. Explain CMOS operation regions
2. Sizing of 2 input NAND Gate
3. difference between blocking and Non-blocking(Verilog)
4. What are arrays and Hashes in PERL

Selected for On-site with 1:1 round with 7 Engineers
1. He drew digital circuits with basic Gates and the delays and asked to draw waveforms
2. C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question)
3 & 4. Asked on my Resume and Research work
5. Asked me more in detail about CMOS like why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc
6. Director discussed more about the company
7. Asked about Flip Flops and setup hold time and Max Frequency of a sequential and Combinational circuit

Interview Questions

  • He drew digital circuits with basic Gates and the delays and asked to draw waveforms   Answer Question
  • why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc   View Answer
  • C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question)   View Answer
  • Flip Flops and setup hold time and Max Frequency of a sequential and Combinational circuit   Answer Question

Negotiation Details – No Negotiation as I am a Fresh Grad

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1 person found this helpful

No Offer

Neutral Experience

Average Interview

High Speed I/O Interview

High Speed I/O
San Jose, CA

I applied online and the process took 2 weeks - interviewed at Dolphin Technology Inc in March 2013.

Interview Details – Applied on line. Got a email to schedule a phone interview very soon. One phone interview related to the resume, took about 20 mins. A week later went to the in-person interview. Four round, two of them were focus on the digital logic question. Inverter , FF and the advantages and disadvantages about the FF, set up time and hold time, latch up; One is focus on the C; The last one was asking analog question. CS, Ids and current mirror.

Interview Question – cons and pros about the FF you have drawn. Comparing with other schematic.   View Answers (5)

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2 people found this helpful

No Offer

Neutral Experience

Average Interview

Circuit Design/Analog Mixed Signal Design (Multiple Positions Available) Interview

Circuit Design/Analog Mixed Signal Design (Multiple Positions Available)
San Jose, CA

I applied online and the process took 5 days - interviewed at Dolphin Technology Inc in March 2013.

Interview Details – The whole process is it: I received the call from the company after I submit the resume. They schedule the on-site interview directly. They comes with different people from different group. First person ask about inverter and then NAND gate, and how to size them to make rise time and fall time equally. Then ask about the verilog question. Second person draw a pics with four different circuit about the circuit and asked when the clock comes in what the output will be. And then ask about the passgate flip-flop. The third one asked C programming and he gave me a test sheet to write up.

Interview Questions

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2 people found this helpful

No Offer

Neutral Experience

Easy Interview

Circuit Design Engineer Interview

Circuit Design Engineer
Santa Clara, CA

I applied online and the process took 2 weeks - interviewed at Dolphin Technology Inc in January 2012.

Interview Details – I was called in for the interview, was notified that it might take 4 hours at the most but completed in 1 hour and a bit more. The HR manager was a lady, asked me to explain any of my favorite projects, I did, then went on to next round, technical round, asked a few questions regarding verilog, write the code for D filpflop and some Vlsi basic stuff.

Interview Question – Explain about your projects?
Verilog
D_ff
D_latch
Asked to draw a Nand gate schematic?
Convert the nand gate to inverter?
Inverter sizes?
  Answer Question

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