Elsys Design Interview Questions & Reviews
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Design Verification Engineer at Elsys Design
Posted Aug 15, 2011
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2.0
Easy Interview
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Overall Positive Experience
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Received and Accepted Offer
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Interviewed Feb 2009 in Belgrade (Serbia) (took a day)
The interview consisted of going through the CV, with the solving of one simple problem in the HDL design.
The interviewer asked questions about the problems I had to solve for each project I've listed.
Needed experience was HDL design and good C knowledge, as well good knowledge of English (standard requirements, nothing special).
Interview Questions
Create a simple module in VHDL or Verilog, with some basic functionality
Other Details
The interview consisted of a 1:1 Interview.
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