View All num of num See all Photos Micron Technology This employer has taken extra steps to respond to reviews and provide job seekers with accurate company information, photos, and reviews. Interested for your company?Learn More. www.micron.com Employer Engaged Overview Reviews Salaries Interviews Jobs Photos Benefits 541 Reviews 2.3k Salaries 234 Interviews Follow Add Review or Salary Follow Add Review or Salary Interview Question Product Engineer Interview(Student Candidate) Boise, ID Micron Technology Given: three clamped NMOS transistors in series with Vcc at the beginning. The output of the final one went into the source of a PFET, with the drain tied to ground and the gate tied to some voltage, I forget exactly what. I was asked to label the voltage at each node, and then which state the PFET was in. Tags: See more , See less 8 Answer Add Tags Answer Interview Answer 3 Answers ▲ 1 ▼ Each NMOS transistor dropped Vcc down by .7v due to VT drop for a total drop of 2.1v. I don't remember what the gate of the PFET was at, but the voltages were such that the state was unexpected.Sorry for the cruddy recollection, but it was awhile ago. Interview Candidate on Feb 8, 2012 ▲ 0 ▼ Just to add to the above remark, NMOS when ON does not pass a good High Voltage, the source side is always Vth below the gate voltage (ensuring ON state). Assuming Vth is 0.7V and the 3 NMOS are ON using VDD the net drop across the 3 transistors is VDD - (3 x 0.7) = VDD - 2.1Depending on VDD and Gate voltage at PMOS you can come up with its state. NCG (ASU) on Jun 15, 2012 ▲ 2 ▼ if all gates of NMOS are connected to Vdd then it'll only degrade once which is Vdd-Vtn for the first NMOS, for the rest of two NMOS it can pass the full Vdd-Vtn Han on Jun 28, 2012 Add Answers or Comments To comment on this, Sign In or Sign Up.