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Intel Corporation Component Design Engineer Interview Questions & Reviews in Oregon

Updated Mar 27, 2014
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Component Design Engineer Interview

Component Design Engineer
Hillsboro, OR

I applied through college or university and the process took 1 week - interviewed at Intel Corporation in July 2012.

Interview Details – The interview lasted from 9am to 4pm, total 6 rounds with three different teams. The interview tested both HW & SW. HW includes timing & delay analysis, RTL coding, FSM design, basic gate topology and leakage, pass gates.etc. SW includes string manipulation, decimal to hex conversion&recursion. Both C & perl were used. In the end, I met with the hiring manager for a wrap up.

Interview Question – Design an FSM that can generate a single pulse after certain no. of rising clk edge. Such no. is defined by the input.   Answer Question

Negotiation Details – Dream company + dream team, didn't negotiation at all.

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