Linear Technology Interview Questions & Reviews

Interviewed Feb 2011 in Cary, NC (took a day)

Application date was Jan 14, email follow-up by site manager Feb 10, to discuss position. After the initial discussion, I requested to talk in person, and the manager agreed I could come in the following week. It was not clear at the time that I had a full-blown interview, because a formal interview was not mentioned nor was the time required for the interview (5 hours) or the number of people I would talk to. Perhaps a communication lapse? No matter, I was happy to have the opportunity.

The interview started at 9:00 am and I left the premises at about 2:15 pm.

The interview consisted of a series of one-on-ones with the site manager, a design engineer, a design team manager, a design team leader and two layout designers.

The manager asked preliminary questions to clear up areas of confusion or inconsistency on my resume, then we proceeded to a conference room where I was asked technical questions about analog layout. The topics included: Lateral BJT device design, MOSFET device design, CMOS device design, BiCMOS device design, JFET device design, basic thin film resistor design, MOS capacitor design, isolation wells, reverse bias (depletion isolation) design practices, fundamentals of parasitic latch-up devices, simple NMOS and PMOS design with one or two transistors, identification of devices by symbol and the obligatory Ohm's law. All designers used color layout plots to ask questions, asking me to identify basic devices and features, such as BJTs and location of well ties.

Impressions: Design engineers very competent, asked questions like grad students giving ungraded pop quiz to undergrad lab students. So, they were easy going, but to the point.

Advice: Know that they use LATERAL BJT devices. If you are unfamiliar with analog physical design or are rusty, get ahold of a picture or a working design and study it. Practice identifying NPN, PNP, isolation wells and all well and substrate ties. They use analogy symbols for MOS devices, so if you are used to dealing with the simplified digital depictions, study up on the various symbols used in analog.

After the designers, it was a sit-down test at a workstation with a layout designer standing and looking over my shoulder. I was asked to use Cadence XL to layout two simple designs implemented in PCELLS. The first design used BJTs, the second design used CMOS devices.

Impressions: Stressful, cold, clinical assessment of CAD tool familiarity and layout design skill.

Advice: Know Cadence XL, and do not make any mistakes related to layout. Lay out the CMOS circuit tight, as if it was a standard cell.

Sandwich lunch followed with the site manager and another layout designer. Site manager generously paid for all. After that it was a low-key one-on-one with the second layout designer where the discussion was left rather open-ended.

The interview was completed by a wrap-up discussion with the site manager. I was informed via email the morning after that I had not been selected.

Office was in an older building (20 years) and workers were clearly responsible for their own workspace cleanliness and neatness, so this varied according to particular office or cubicle. Kitchenette was standard with coffee, tea, hot water, sink and fridge. Restroom (Men's) was clean.

Overall impression: Small office, few levels of hierarchy, very casual but busy with lots of work.