Link A Media Devices
Link A Media Devices Interview Questions & Reviews in San Jose, CA
Getting an Interview
Senior ASIC Design Engineer Interview (Neutral Experience; Difficult Interview)
I applied online and the process took 1+ week - interviewed at Link A Media Devices.
Interview Details – Phone interview, followed by an on-site interview
Interview Question – design async-fifo and sync-fifo in circuit level Answer Question
Design Engineer Interview (Neutral Experience; Average Interview)
I applied online and the process took 2 weeks - interviewed at Link A Media Devices in April 2012.
Interview Details – Some time in between the conversation I felt the communication problem as all the interviewers were Asians and it was hard to keep up with them sometimes only.
Interview Question – One of the question was a combinatinal circuit and the othe unexpected question was ; why did you took so much time to complete this project? Answer Question
Junior ASIC Design Engineer Interview (Neutral Experience; Easy Interview)
I applied online and the process took a day - interviewed at Link A Media Devices in November 2011.
Interview Details – All of the questions are technical, such as:
draw a 2-bits counter using dff or other gate
Design a FSM to detect sequence 1101
Verification Engineer Interview (Neutral Experience; Average Interview)
I applied online and the process took a day - interviewed at Link A Media Devices in July 2010.
Interview Details – I was called to arrange a time for a phone interview. The actual interview sounded like I was on a speakerphone and there were others in the room besides the person asking the questions. The interviewer never told me his role in the company, what the company did, what exactly they were looking for, what projects I've worked on, just started asking interview questions. It took about an hour.
- how deep of a FIFO do i need in the following case:
for every 100 clock cycles, 80 clock cycles are writes
for ever 10 clock cycles, 8 clock cycles are reads
assume the clocks are the same View Answer
- assume i have a memory controller. it talks to dram/flash/etc and has a host configuration interface. the memory controller arbitrates among 3 inputs. if you were to model a requester, what info would it need to provide to the memory controller Answer Question
- if i have a system with n pipeline cycles, under what conditions will i have the worst latency and how can you minimize the latency. Answer Question
- can you get higher utilization in an ASIC or FPGA? Answer Question
- what sort of issues would you run into when you design for an FGPA vs an ASIC Answer Question