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Interview Question

ASIC Design Engineer Interview Hillsboro, OR

List all possible ways to minimize the power dissipation of

  an ASIC chip.
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2 Answers

2

break down this question first into two aspects:
Pdyn and Pstat (dynamic power and static power)
dynamic power caused by switching activity
static power caused by leakage and whatnot

-change threshold voltage of transistors. lower threshold voltage, less power dissipation. tradeoff: more susceptible to noise, more unstable, may have to use higher nominal voltage
-clock gating: add a simple AND gate (simplest method) to a branch on the clock distribution network to basically turn off clock on flip flops. people use this because clock dissipates a lot of switching power, which is a component of dynamic power.
-multi-vdd design: probably most promising method... partition your CPU into different voltage areas so that certain physical areas of the chip can power down or up to different voltages when idle or busy. You need level shifters to implement this...
-power gating: goes hand in hand usually with multi-vdd design. Idle areas of the chip can be powered down completely sometimes. You need isolation gates for this...
-dynamic frequency-voltage scaling (voltage regulation): think of overclocking your computer. for example, if you overclock your CPU by 10%, you may need 13% increase in your VDD. Similarly, maybe an idle portion of the CPU only needs an operating frequency of 1Ghz as opposed to 2.6GHz. In asic design, usually this highly analog component can be black boxed as hard IP and inserted into ur asic design.

Means to implement these power dissipation techniques:
theres been huge leaps done in industry recently (past decade) by Intel and other asic design companies as well as IEEE to standardize multi voltage design and power gating. look at UPF and CPF languages. UPF is standardized by IEEE and basically lets desginers write a separate input file called a power intent file that goes along with RTL into synthesis, verification, and layout tools. what this means is partitioning different logical and physical areas of the asic chip by power supply. for example, maybe your FPC needs 2.5V but your clock management unit needs 3V.

moaxgeni on Sep 11, 2012
0

To clarify, if you use power gating =/= clock gating. if you use power gating on a voltage area, you are gating the power supplies into that block... think Vdd and Vss, ie you are also turning power off to the that subnetwork of clocks. if you are clock gating, you are gating just the clock, but the flop is still connected to power. this means that if you use power gating, you may need to implement retention flops if you have any flip flops in your power gated block.

in summary, the effect of clock gating usually is a subset of the effects of power gating. that's why power gating is much more effective.

moaxgeni on Sep 11, 2012

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