Getting an Interview
Getting an Interview
Interviews for Top Jobs at Marvell Technology
- ASIC Design Engineer (37)
- Software Engineer (12)
- Design Verification Engineer (9)
- Engineering (9)
- Logic Design Engineer (7)
- Design Engineer (6)
- Verification Engineer (5)
- Test Engineer (4)
- Applications Engineer (4)
- Physical Design Engineer (4)
- Analog Design Engineer (4)
- ASIC Verification Engineer (4)
- Staff Design Engineer (3)
- Hardware Engineer (3)
- Senior Design Engineer (3)
- Firmware Engineer (3)
- Validation Engineer (3)
- Software Developer (2)
- Engineer (2)
- Digital Design Engineer (2)
- Digital IC Design Engineer (2)
- Product Marketing Manager (2)
- Senior ASIC Design Engineer (2)
- CAD Engineer (2)
- Associate Software Engineer (2)
- Lawyer (1)
- Contract Software Engineer (1)
- Summer Intern (1)
- Systems Design Engineer (1)
- Systems Engineer (1)
- No OfferPositive ExperienceAverage Interview
I got a phone interview the other day directly from a current employee from their CPU group. He asked me about the basic concepts in computer architecture and it was not very hard. Also, he asked a lot about work experiences showed on my resume.
- basic cache related questions Answer Question
- Declined OfferPositive ExperienceAverage Interview
I applied through an employee referral. The process took 2 weeks. I interviewed at Marvell Technology (Santa Clara, CA) in September 2015.
The first round was a phone interview of around 45 minutes. Focused entirely on linear pipeline and Out of Order Pipeline principles. The second round was a face to face interview at Santa Clara. 4.5hrs of interview (45 minutes per interviewer), was completely technical focussing on FSm, Verilog design, Cache and Tomasulo Out of order implementation.
- 1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines. 2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design. One of the interviewers gave a scenario and asked to wite a code to validate the integrity of the circuit (to test our VERIFICATION thinking ). Answer Question
- No OfferNeutral ExperienceAverage Interview
I applied online. The process took 1+ week. I interviewed at Marvell Technology (Ann Arbor, MI) in August 2015.
I apply online for intern. It took around 10 days to get the email to tell I took 30 min interview for the intern. The question is all about cache part. I didn't prepare very well. Some question I answered is not quite well.
- explain about cache Answer Question
- Accepted OfferPositive ExperienceAverage Interview
I applied online. I interviewed at Marvell Technology.
Phone interview for very basic digital design question i.e. setup/hold time, max clock frequency, and some project questions. Received onsite interview after 2 weeks, asked very detailed on my verilog project, fsm, fifo, cross domain clock, little perl and OOP.
- never learned perl before so did not answer. 1 Answer
- Declined OfferAverage Interview
I applied through college or university. The process took 2+ months. I interviewed at Marvell Technology.
I applied through school career fair and I got called for an onsite interview in about a month. The questions were average difficulty. It varied slightly by the person who was interviewing.
- They asked general processor design questions. Answer Question
Reasons for Declining
I had a better offer from another company
- No OfferPositive ExperienceAverage Interview
I applied through an employee referral. The process took a week. I interviewed at Marvell Technology (Santa Clara, CA) in December 2014.
phone interview -- just general question because i got refer from my friends onsite interview -- got me email from HR to arrange my interview date and time i had 5 people for interview most of them were nice, but one guy was very annoying. i coudn't understand his question, so i asked again. but he was angry because i asked again. had a lunch with them and talk about general question
- clock divider / mealy vs moor fsm / through my resume project / setup time hold time Answer Question
- Accepted OfferPositive ExperienceEasy Interview
I applied through an employee referral. The process took a week. I interviewed at Marvell Technology (Santa Clara, CA).
Phone call from HR, tell details about grounp, and On-Site with 7 rounds, each round takes 45 mins, 1:1 style, Very basic question, setup, hold, timing report, Manager took for lunch, and talk about the group, and visit campus. Logic effect calculation, draw stick picture of NAND, sample sequence detector, cross clock domain. Talk about your resume, and explain your project at school. Nothing surprises, pretty basic stuff.
- How to deal with MCMM opt Answer Question
- No OfferNeutral ExperienceDifficult Interview
I applied online. The process took 2 weeks. I interviewed at Marvell Technology (Santa Clara, CA) in November 2014.
apply online and after several weeks, I got phone interview. It is about ASIC design/verification. My background is more focus on Verification of microprofessor, FPGA. Not very familiar with ASIC flow.so it is very important for background match.
- ASIC flow, setup/hold, fix violation Answer Question
- No OfferNegative ExperienceAverage Interview
I applied online. The process took 3+ months. I interviewed at Marvell Technology (Santa Clara, CA) in November 2014.
I received a call for an onsite interview as I was in Santa Clara itself. I gave first onsite with 3 engineers. After 15-20 days I received call for another onsite with 4 engineers. The interviews were pretty basic stuff related to Verilog basics, FSM Design, FIFO related questions as well as on the resume. After 2nd onsite I waited for 2 months but I did not get any reply from HR or recruiter. Finally when I contacted manager, I was told that they had already selected some other candidate. They seriously should learn some professionalism and have the courtesy to give an update to someone who gave 2 onsite interviews. Totally disappointed with the process speed as well communication.
- Verilog tasks and functions, FSM Design, FIFO Depth, some system verilog questions. Answer Question
- Accepted OfferNeutral Experience
the process is typical can nice. started with phone interview, then go in site for interview. There was 4~5 hiring manager interviewing and followed by lunch interview with Director. Finish with VP. The whole process takes 6 hours.
- all technical questions none was difficult for me Answer Question
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