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Marvell Technology Verification Engineer Interview Questions & Reviews

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Updated Mar 13, 2012 – Interview questions and reviews posted anonymously by interview candidates.

Difficulty Rating [?] Based on 4 ratings

3.5

“Difficult” Interview

Interview Experience [?] Based on 4 ratings

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Neutral	50%
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1–4 of 4 Marvell Technology Interviews

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3.0

Average Interview

Overall Positive Experience

Received and Accepted Offer

Interviewed Aug 2011 in Santa Clara, CA (took a day)

Quiz and 1:1 with potential team members

Interview Questions

Pipelining, FSM pattern generator, Digital logic (simple)

Answer Question

Perl questions, Propose test plan for round robin arbiter

Answer Question

Other Details

I Applied Online and the interview consisted of a 1:1 Interview.

Helpful Interview?

Yes | No

Inappropriate?

3.0

Average Interview

Overall Positive Experience

Received and Declined Offer

Interviewed Jan 2012 (took a day)

there are 7 people doing 1:1 interview during the day. first HR, and then technique questions. Before onsite interview, they did a phone interview to me to check my academic background. and asked me to write some system verilog assertions, then asked some common questions about set up time and hold time

Interview Questions

advantages of mealy and moore

Answer Question

if you have 2 masters and 4 slaves, what properties can you write to check the function?

Answer Question

describe MIPS CPU

Answer Question

write merge sort in C code

Answer Question

Other Details

I Applied Online and the interview consisted of a Phone Interview and a 1:1 Interview.

Helpful Interview?

Yes | No

Inappropriate?

3.0

Average Interview

Overall Neutral Experience

Interviewed and No Offer

Interviewed Jul 2010 in San Jose, CA (took a day)

A phone interview first. Asked to describe work history and offered job description.
A long employment application filled out online, printed out and bring to on-site interview.

The perception I gathered from the interview is that Marvell did not emphasize on verification and in the process of rectifying that. One engineer warned me that I should expect resistance of forcing verification methodology on the teams if I were to be offered and accept the job.

Interview Questions

a piece of systemVerilog code regarding fork/join_none and explain its behavior
(the following code is not exact)

module ...
fork
  for (i=0; i<16; i++) begin
    $display("%d\n", i);
    #1
  end
join_none
endmodule

output:
0
1
2
.
15

simulation ends at time 0

Q: why it ends at time 0, where does #1 go?

Answer Question

C questions:
- array vs pointer
- passed by value/reference

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