NVIDIA

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# NVIDIA ASIC Intern Interview Questions

7 Interview Reviews

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## 7 Candidate Interview Reviews Back to all Interviews

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## ASIC Intern Interview

No Offer
Positive Experience
Average Interview

Application

I applied through an employee referral – interviewed at NVIDIA in March 2013.

Interview

Attended first round, going to attend second and third rounds. ASIC intern at Santa Clara.

Interview Questions

• Design xor2 gate using two 2-input muxes, inputs A and B, power and ground.   1 Answer
• Setup and hold time - definitions; there is a branch with one path being setup critical, and another with a hold violation. Given a buffer, where will you place it if both paths should not have violations?   Answer Question
• Where are gray counters used?   Answer Question
• Design xor2 gate using only nand2 gates   Answer Question
• 4 men, 1 bridge, can cross 2 at a time, only 1 flashlight. Each one takes 1,2,5,10 minutes to cross one way. Minimum time for all 4 to cross bridge.   3 Answers

1.

## ASIC Intern Interview

No Offer
Average Interview

Application

I applied through college or university. The process took a weekinterviewed at NVIDIA in March 2013.

Interview

1 Interview - 1 question on state machines, 1 river crossing riddle, 1 question on logic design

Interview Questions

2.

## ASIC Intern Interview

Accepted Offer
Positive Experience

Application

I applied through college or university. The process took 2+ monthsinterviewed at NVIDIA (Santa Clara, CA) in November 2012.

Interview

Interview call from career fair. 3 phone interview rounds

Interview Questions

## ASIC Intern Interview

No Offer
Positive Experience
Difficult Interview

Application

I applied online. The process took 5+ weeksinterviewed at NVIDIA (Santa Clarita, CA) in March 2012.

Interview

3 Interview on Phone

Interview Questions

• Round 1
1- Two to Three Q's on Projects done
2- Designing Q - Consider inputs coming at every clock. I want the output at time = t to give me sum of all nos coming before that time. (Adder is normal adder with latency 1)
3- Designing Q - Consider the same output needed, but adder has a latency of 2. So input is taken at every clock and output is given at every clock. But Input at t=0 is received at output at t=2, input at t=1 is received at output at t=3...

• Round 2
1- RTL coding
2- C, C++ pointer questions
3- how to do VHDL coding
4- FSM Sequence detector
5- How will you verify the FSM code
6- Design Using Shift Registers
7- How will you code this

• Round 3
2- two Pipelines runnign parallely. 128 Bit register file. 4 read ports n 2 write ports. Convert it into 4 reg files with one read n one write ports for all. Find adv and dis adv.
3- Design a divide by 3 FSM checker

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5.

## ASIC Intern Interview

No Offer

Interview

Phone interview
Design gates using CMOS transistors.
Build gates using 2-to-1 muxes.
Write a verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency.
The number of states required for a sequence recognizer.

Interview Questions

• Phone interview
Design gates using CMOS transistors.
Build gates using 2-to-1 muxes.
Write a verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency.
The number of states required for a sequence recognizer.

6.

## ASIC Intern Interview

No Offer

Interview

45min phone interview. I talked about 2 projects in my resume. then the interviewer give me some quiz to solve.

Interview Questions

7.

## ASIC Intern Interview

No Offer
Positive Experience
Difficult Interview

Application

The process took 2+ monthsinterviewed at NVIDIA in January 2010.

Interview

4 Levels of Interview. Extremely Technical. Not one question was behavioral.

Interview Questions

## NVIDIA

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