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Interview Question

CPU Design Verification Engineer Interview Raleigh, NC

Pipelining Hazards?

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Interview Answer

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Hazards are problems with the instruction pipeline in CPU micro-architectures, when the next instruction cannot execute in the following clock cycle and can potentially lead to incorrect computation results. There are typically three types of hazards

data hazards
structural hazards
control hazards (branching hazards)

  There are several methods used to deal with hazards, including pipeline stalls/pipeline bubbling, operand forwarding, and in the case of out-of-order execution, the scoreboarding method and the Tomasulo algorithm.

Source:Wiki

Navin Senguttuvan on Feb 19, 2015

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