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Interview Question

Engineering Interview

Plan a logical design which gets a single read/write bit

  every clock cycle, and a number. The design should store the histogram of the written input, and display it on a read command.
Answer

Interview Answer

1 Answer

0

A duel port ram which reads the address, and in a write cycle adds +1 to it's value with a counter. Counter connected to the ram again the following cycle to write the new value.

Interview Candidate on Oct 4, 2011

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