Qualcomm
3.9 of 5 1,260 reviews
www.qualcomm.com San Diego, CA 5000+ Employees

Qualcomm ASIC Design Engineer Interview Questions & Reviews

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Interview Experience 

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7 candidate interviews Back to all interview questions
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No Offer

Neutral Experience

Average Interview

ASIC Design Engineer Interview

ASIC Design Engineer
San Diego, CA

I applied online and the process took a day - interviewed at Qualcomm in April 2012.

Interview Details – it's a long interview from 9:30 am to 4:50 pm.there are 6 interviewers.the first one just ask for you information. the other 5 interviewers asked technique question. they were asking me questions even when I was having lunch. It's a long day. So be prepared. Sleep well the night before.

Interview Question – what 's the steps of synthesis?   View Answer

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Accepted Offer

Positive Experience

Average Interview

ASIC Design Engineer Interview

ASIC Design Engineer
San Diego, CA

I applied through college or university and the process took a day - interviewed at Qualcomm in November 2012.

Interview Details – great experience. Had an awesome interview . more like a holiday , 3 rounds of interview , digital, verilog, and verification. awesome accomodation.

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No Offer

Neutral Experience

Easy Interview

ASIC Design Engineer Interview

ASIC Design Engineer
San Diego, CA

I applied through college or university and the process took a day - interviewed at Qualcomm in March 2010.

Interview Details – Questions about designing Logic modules using gates and transistors. Questions about setup time, hold time etc. Design problem as pattern recognizer design. Interviewed by a non-native america, weird accent.

Interview Question – Using only NAND gate to design some logic   View Answer

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Accepted Offer

Neutral Experience

ASIC Design Engineer Interview

ASIC Design Engineer

Interviewed at Qualcomm

Interview Details – 2 on campus interview. They will ask question based on your resume. As for me, they ask some questions on C++, verilog, computer architecure techniques. After interview, they inform me of the offer on the next week. Then they help me process the accommodation, offer acception form and so on.

Interview Question – Write the verilog of ROB on a paper.   Answer Question

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Declined Offer

Neutral Experience

Average Interview

ASIC Design Engineer Interview

ASIC Design Engineer
Bangalore (India)

I applied through an employee referral and the process took 2 days - interviewed at Qualcomm in October 2009.

Interview Details – 1 telephone prelimnary interview
4 rounds of face to face technical interview no hr round
all 4 interviews done in single day
result announced in 2 days
interviews included questions on STA, synthesis, RTL coding and a few aptitude questions
each interview was for about an hour each
RTL design questions were related to AXI protocol as they were looking for Soc integration position

Interview Question – using a simple logic gate, convert a SET type flop to a RESET type flop   View Answer

Reason for Declining – only 10% salary raise offered

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1 person found this helpful

No Offer

Positive Experience

Difficult Interview

ASIC Design Engineer Interview

ASIC Design Engineer

I applied through an employee referral and the process took a day - interviewed at Qualcomm in March 2012.

Interview Details – Asked questions about synchronization between different clock domains, setup and hold time, low power design techniques, and a few Verilog questions

Interview Questions

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1 person found this helpful

No Offer

Neutral Experience

Difficult Interview

ASIC Design Engineer Interview

ASIC Design Engineer

I applied through college or university and the process took 1 week - interviewed at Qualcomm in October 2011.

Interview Details – Resume was shortlisted and I was called for the interview. 2 rounds of Technical Interview for Design & Verification. Verification Interview was on state machine design, Verilog coding & scheduling problems. Should be easy if you are strong in Digital Eletronics. Design Interview was standard. The interviewer asked me to design an Asynchronous FIFO; False paths, Multi-Cycle paths; Clock Domain Conversion; 1 bit transfer between 2 different clocks; Metastability etc..

Interview Question – False paths and Multiple cycle path examples.   Answer Question

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