Getting an Interview
Getting an Interview
Interviews for Top Jobs at Qualcomm
- Software Engineer (160)
- Intern (66)
- Senior Software Engineer (35)
- Engineer (34)
- Embedded Software Engineer (32)
- Engineering (26)
- Senior Engineer (19)
- Hardware Engineer (18)
- Software Engineer Intern (18)
- Systems Engineer (18)
- Verification Engineer (17)
- Interim Engineering (16)
- Test Engineer (15)
- Systems Test Engineer (14)
- Internship (12)
- Associate Engineer (11)
- Senior Systems Engineer (10)
- Interim Engineering Intern (10)
- Staff Engineer (9)
- Staff Software Engineer (9)
- ASIC Design Engineer (9)
- Design Engineer (9)
- Digital Design Engineer (9)
- Modem Systems Test Engineer (7)
- Design Verification Engineer (6)
- Program Manager (6)
- Modem Test Engineer (6)
- DSP Firmware Engineer (5)
- Software Engineering (5)
- Embedded Software Developer (5)
ASIC Design Engineer Interview
Phone interview followed by onsite. Total process took about a month. Phone interview for 45 min. Onsite interview was lengthy with 6 different people for 1 hr each. Got the offer in 2 weeks after the onsite interview.
- Questions on Flip-flops, tristate buffer, logic design Answer Question
Other Interview Reviews for Qualcomm
ASIC Design Engineer InterviewNo OfferNegative ExperienceEasy Interview
I applied online – interviewed at Qualcomm (San Jose, CA) in March 2013.
Direct on-site with out phone interview at Atheros
- Everything was easy. Counter Design using Moore Machine, Counter Code in verilog, Clock Domain Crossing Questions and MCP in PT Answer Question
ASIC Design Engineer InterviewAccepted OfferPositive ExperienceAverage Interview
I applied through college or university. The process took 1 day – interviewed at Qualcomm (San Diego, CA) in November 2012.
great experience. Had an awesome interview . more like a holiday , 3 rounds of interview , digital, verilog, and verification. awesome accomodation.
ASIC Design Engineer InterviewNo OfferNeutral ExperienceAverage Interview
I applied online. The process took 1 day – interviewed at Qualcomm (San Diego, CA) in April 2012.
it's a long interview from 9:30 am to 4:50 pm.there are 6 interviewers.the first one just ask for you information. the other 5 interviewers asked technique question. they were asking me questions even when I was having lunch. It's a long day. So be prepared. Sleep well the night before.
- what 's the steps of synthesis? 1 Answer
ASIC Design Engineer InterviewNo OfferNeutral ExperienceEasy Interview
I applied through college or university. The process took 1 day – interviewed at Qualcomm (San Diego, CA) in March 2010.
Questions about designing Logic modules using gates and transistors. Questions about setup time, hold time etc. Design problem as pattern recognizer design. Interviewed by a non-native america, weird accent.
- Using only NAND gate to design some logic 1 Answer
ASIC Design Engineer InterviewAccepted Offer
2 on campus interview. They will ask question based on your resume. As for me, they ask some questions on C++, verilog, computer architecure techniques. After interview, they inform me of the offer on the next week. Then they help me process the accommodation, offer acception form and so on.
- Write the verilog of ROB on a paper. Answer Question
ASIC Design Engineer InterviewNo OfferPositive ExperienceDifficult Interview
I applied through an employee referral. The process took 1 day – interviewed at Qualcomm in March 2012.
Asked questions about synchronization between different clock domains, setup and hold time, low power design techniques, and a few Verilog questions
ASIC Design Engineer InterviewNo OfferNeutral ExperienceDifficult Interview
I applied through college or university. The process took a week – interviewed at Qualcomm in October 2011.
Resume was shortlisted and I was called for the interview. 2 rounds of Technical Interview for Design & Verification. Verification Interview was on state machine design, Verilog coding & scheduling problems. Should be easy if you are strong in Digital Eletronics. Design Interview was standard. The interviewer asked me to design an Asynchronous FIFO; False paths, Multi-Cycle paths; Clock Domain Conversion; 1 bit transfer between 2 different clocks; Metastability etc..
- False paths and Multiple cycle path examples. Answer Question
ASIC Design Engineer InterviewDeclined OfferAverage Interview
I applied through an employee referral. The process took 2 days – interviewed at Qualcomm (Bangalore (India)) in October 2009.
1 telephone prelimnary interview 4 rounds of face to face technical interview no hr round all 4 interviews done in single day result announced in 2 days interviews included questions on STA, synthesis, RTL coding and a few aptitude questions each interview was for about an hour each RTL design questions were related to AXI protocol as they were looking for Soc integration position
- using a simple logic gate, convert a SET type flop to a RESET type flop 1 Answer
Reasons for Declining
only 10% salary raise offered
Is this helpful? The community relies on everyone sharing – Add Anonymous Interview Review