Qualcomm ASIC Design Engineer Interview Questions

9 Interview Reviews

Interview Experience

Interview Experience

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Helpful (3)  

ASIC Design Engineer Interview

Anonymous Employee
Declined Offer

Interview

Phone interview followed by onsite. Total process took about a month. Phone interview for 45 min. Onsite interview was lengthy with 6 different people for 1 hr each. Got the offer in 2 weeks after the onsite interview.

Interview Questions

  • Questions on Flip-flops, tristate buffer, logic design   Answer Question

Other Interview Reviews for Qualcomm

  1. Helpful (6)  

    ASIC Design Engineer Interview

    Anonymous Employee in San Jose, CA
    No Offer
    Negative Experience
    Easy Interview

    Application

    I applied online – interviewed at Qualcomm (San Jose, CA) in March 2013.

    Interview

    Direct on-site with out phone interview at Atheros

    Interview Questions

    • Everything was easy. Counter Design using Moore Machine, Counter Code in verilog, Clock Domain Crossing Questions and MCP in PT   Answer Question
  2.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in San Diego, CA
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied through college or university. The process took 1 dayinterviewed at Qualcomm (San Diego, CA) in November 2012.

    Interview

    great experience. Had an awesome interview . more like a holiday , 3 rounds of interview , digital, verilog, and verification. awesome accomodation.

  3.  

    ASIC Design Engineer Interview

    Anonymous Employee in San Diego, CA
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied online. The process took 1 dayinterviewed at Qualcomm (San Diego, CA) in April 2012.

    Interview

    it's a long interview from 9:30 am to 4:50 pm.there are 6 interviewers.the first one just ask for you information. the other 5 interviewers asked technique question. they were asking me questions even when I was having lunch. It's a long day. So be prepared. Sleep well the night before.

    Interview Questions

    • what 's the steps of synthesis?   1 Answer
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  5.  

    ASIC Design Engineer Interview

    Anonymous Employee in San Diego, CA
    No Offer
    Neutral Experience
    Easy Interview

    Application

    I applied through college or university. The process took 1 dayinterviewed at Qualcomm (San Diego, CA) in March 2010.

    Interview

    Questions about designing Logic modules using gates and transistors. Questions about setup time, hold time etc. Design problem as pattern recognizer design. Interviewed by a non-native america, weird accent.

    Interview Questions

    • Using only NAND gate to design some logic   1 Answer
  6.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate
    Accepted Offer

    Interview

    2 on campus interview. They will ask question based on your resume. As for me, they ask some questions on C++, verilog, computer architecure techniques. After interview, they inform me of the offer on the next week. Then they help me process the accommodation, offer acception form and so on.

    Interview Questions

  7. Helpful (2)  

    ASIC Design Engineer Interview

    Anonymous Employee
    No Offer
    Positive Experience
    Difficult Interview

    Application

    I applied through an employee referral. The process took 1 dayinterviewed at Qualcomm in March 2012.

    Interview

    Asked questions about synchronization between different clock domains, setup and hold time, low power design techniques, and a few Verilog questions

    Interview Questions

    • How to bring a signal from one clock domain to another   1 Answer
    • Describe several methods for low power design   Answer Question
  8. Helpful (1)  

    ASIC Design Engineer Interview

    Anonymous Employee
    No Offer
    Neutral Experience
    Difficult Interview

    Application

    I applied through college or university. The process took a weekinterviewed at Qualcomm in October 2011.

    Interview

    Resume was shortlisted and I was called for the interview. 2 rounds of Technical Interview for Design & Verification. Verification Interview was on state machine design, Verilog coding & scheduling problems. Should be easy if you are strong in Digital Eletronics. Design Interview was standard. The interviewer asked me to design an Asynchronous FIFO; False paths, Multi-Cycle paths; Clock Domain Conversion; 1 bit transfer between 2 different clocks; Metastability etc..

    Interview Questions

  9. Helpful (2)  

    ASIC Design Engineer Interview

    Anonymous Employee in Bangalore (India)
    Declined Offer
    Average Interview

    Application

    I applied through an employee referral. The process took 2 daysinterviewed at Qualcomm (Bangalore (India)) in October 2009.

    Interview

    1 telephone prelimnary interview 4 rounds of face to face technical interview no hr round all 4 interviews done in single day result announced in 2 days interviews included questions on STA, synthesis, RTL coding and a few aptitude questions each interview was for about an hour each RTL design questions were related to AXI protocol as they were looking for Soc integration position

    Interview Questions

    • using a simple logic gate, convert a SET type flop to a RESET type flop   1 Answer

    Reasons for Declining

    only 10% salary raise offered

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