Qualcomm Digital Design Engineer Interview Questions & Reviews

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Digital Design Engineer Interview

Anonymous Interview Candidate
Anonymous Interview Candidate
Application Details

I interviewed online. The process took 4+ weeks - interviewed at Qualcomm.

Interview Details

Starts with a phone interview followed by an onsite interview. Interview is neither complex nor easy. Mainly fundamental Digital Design Questions

Interview Questions
  • I got lot of questions on async designs. Was surprised since was a new grad when I interviewed at Qualcomm, however were not that diffcult to answer. Was surprised there was very little focus on Architecture related questions as compared to other semiconductor companies I have interviewed in the past.   Answer Question
Negotiation Details
I did not negotiate, took the offer as I thought it was competitive.
Accepted Offer
Neutral Experience
Average Interview

Other Interview Reviews for Qualcomm

  1.  

    Digital Design Engineer Interview

    Anonymous Interview Candidate  in  San Jose, CA
    Anonymous Interview Candidate in San Jose, CA
    Application Details

    I interviewed online. The process took 2 weeks - interviewed at Qualcomm.

    Interview Details

    Applied online. Got an email asking if available. Had two rounds of phone interview. Was asked about previous work and projects, no technical questions. Was offered an Intern position and full time at the end of the internship

    Interview Questions
    Accepted Offer
    Positive Experience
    Easy Interview
  2.  

    Digital Design Engineer Interview

    Anonymous Interview Candidate
    Anonymous Interview Candidate
    Application Details

    I interviewed online. The process took 2+ weeks - interviewed at Qualcomm.

    Interview Details

    Consisted of a phone interview followed by an onsite. Phone interview was pretty basic technical questions and questions related to my previous work. Onsite was a pleasurable experience. I was interviewed by 5 different managers or team leads. All interviews were very technical. HR asked some general questions, such as what's your career goal.

    Interview Questions
    • Asynchronous fifos, critical path timing, formal verification, clock gating, hight vt vs low vt   Answer Question
    Accepted Offer
    Average Interview
  3. 1 person found this helpful  

    Digital Design Engineer Interview

    Anonymous Employee  in  San Diego, CA
    Anonymous Employee in San Diego, CA
    Application Details

    I interviewed online. The process took 4+ weeks - interviewed at Qualcomm.

    Interview Details

    Consisted of a phone interview followed by an onsite. Phone interview was pretty basic technical questions and questions related to my current work. Onsite was a pleasurable experience. I was interviewed by 5 different managers or team leads and one HR. All interviews were very technical and true to team's work. HR was interested in knowing what you know about the company.

    Interview Questions
    • Asynchronous fifos, critical path timing, formal verification, clock gating   Answer Question
    No Offer
    Average Interview
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  5.  

    Digital Design Engineer Interview

    Anonymous Employee  in  San Diego, CA
    Anonymous Employee in San Diego, CA
    Application Details

    I interviewed online. The process took a day - interviewed at Qualcomm in April 2012.

    Interview Details

    Interview was very difficult.

    Interview Questions
    • Which parameters are to be considered to choose value of the bypass capacitor   Answer Question
    • Explain stability of the amplifier,   Answer Question
    No Offer
    Positive Experience
    Difficult Interview
  6.  

    Digital Design Engineer Interview

    Anonymous Employee  in  San Diego, CA
    Anonymous Employee in San Diego, CA
    Application Details

    The process took 2+ weeks - interviewed at Qualcomm in June 2011.

    Interview Details

    C++ and he asked some basic digital design question
    one person was mostly asking about asybchronous FIFO.

    Interview Questions
    No Offer
    Neutral Experience
    Difficult Interview
  7. 11 people found this helpful  

    Digital Design Engineer Interview

    Anonymous Employee  in  San Diego, CA
    Anonymous Employee in San Diego, CA
    Application Details

    I interviewed online. The process took 2+ weeks - interviewed at Qualcomm in May 2011.

    Interview Details

    At the start ,I got a phone screen invitation for SOC verification engineer, the phone interview was pretty smooth ,most of the questions were from resume. A few questions on caches ,DMA ,verilog ,pretty basic stuff.
                 About a week later I got an onsite call for the position of Digital Design Engineer New Graduate Positions which I later learned was because my resume was more on the Design side so the verification and Design teams wanted to know where I would be a good fit.Anyway went to the site,it was 7 round interview 3 were with the verification team and the rest with the Design team which I found a little weird. Another thing that struck me as a little odd was that you have to keep moving after every interview ,the interviewer takes you to the next interviewers room where you are asked questions,sometimes the interviewer will keep doing his work which is not a very good experience.Also ,the job description described that they are looking for Digital Designers which can do SRAM,Power Network Design so I thought it would be more transistor level design but it was more of an RTL based design team. I haven't heard from them yet ,but I really don't care .I have a better offer in Austin so I am going to take that.In retrospect Qualcomm is probably a great company to work for if you get the type of job you want to do .The only high point of my day was lunch :) ,I wasn't asked any questions as everyone has mentioned and the food was good.Here are a few questions I can remember
    1)How would you rotate a binary number by a given amount in Verilog?
    2)Divide by two/three circuit,draw state machine to do this task
    3)There is a FIFO ,input is at 100MHZ output is at 80MHZ,At the input ,80 bits arrives every 100 cycles,what should be the size of FIFO so that no data is lost?
    4)Questions on Setup,Hold,two's complement 5)A few basic questions on System verilog like assertions ,interfaces,mailboxes 6)Given seven binary numbers each one bit ,a scheme to add them using minimum number of Full Adders 7)Program to reverse a string in any language you like ,program to find the missing numbers in an array (an array has 1,2,7,8 and the size of array is fixed so the missing numbers here would be 3,4,5,6,7,9 if size of array was 10 10)Reduction using k map,metastability issues
                    This could have been a very easy interview had I known it would be more Verilog and programming stuff.

    Interview Questions
    • Two or Three basic questions on power speed optimization in static CMOS   Answer Question
    No Offer
    Negative Experience
    Average Interview
  8.  

    Digital Design Engineer Interview

    Anonymous Interview Candidate  in  Bangalore (India)
    Anonymous Interview Candidate in Bangalore (India)
    Application Details

    The process took 6 days - interviewed at Qualcomm in January 2011.

    Interview Details

    I had 3 rounds of phone interviews. Very basic questions were asked from Digital logic design. No onsite interview.

    Interview Questions
    Accepted Offer
    Positive Experience
    Easy Interview

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