Qualcomm Digital Design Engineer Interview Questions & Reviews in San Diego, CA
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Digital Design Engineer Interview (Neutral Experience; Average Interview)
I applied online and the process took 4+ weeks - interviewed at Qualcomm.
Interview Details – Consisted of a phone interview followed by an onsite. Phone interview was pretty basic technical questions and questions related to my current work. Onsite was a pleasurable experience. I was interviewed by 5 different managers or team leads and one HR. All interviews were very technical and true to team's work. HR was interested in knowing what you know about the company.
Interview Question – Asynchronous fifos, critical path timing, formal verification, clock gating Answer Question
Digital Design Engineer Interview (Positive Experience; Difficult Interview)
I applied online and the process took a day - interviewed at Qualcomm in April 2012.
Interview Details – Interview was very difficult.
Digital Design Engineer Interview (Neutral Experience; Difficult Interview)
The process took 2+ weeks - interviewed at Qualcomm in June 2011.
Interview Details – C++ and he asked some basic digital design question
one person was mostly asking about asybchronous FIFO.
Digital Design Engineer Interview (Negative Experience; Average Interview)
I applied online and the process took 2+ weeks - interviewed at Qualcomm in May 2011.
Interview Details – At the start ,I got a phone screen invitation for SOC verification engineer, the phone interview was pretty smooth ,most of the questions were from resume. A few questions on caches ,DMA ,verilog ,pretty basic stuff.
About a week later I got an onsite call for the position of Digital Design Engineer New Graduate Positions which I later learned was because my resume was more on the Design side so the verification and Design teams wanted to know where I would be a good fit.Anyway went to the site,it was 7 round interview 3 were with the verification team and the rest with the Design team which I found a little weird. Another thing that struck me as a little odd was that you have to keep moving after every interview ,the interviewer takes you to the next interviewers room where you are asked questions,sometimes the interviewer will keep doing his work which is not a very good experience.Also ,the job description described that they are looking for Digital Designers which can do SRAM,Power Network Design so I thought it would be more transistor level design but it was more of an RTL based design team. I haven't heard from them yet ,but I really don't care .I have a better offer in Austin so I am going to take that.In retrospect Qualcomm is probably a great company to work for if you get the type of job you want to do .The only high point of my day was lunch :) ,I wasn't asked any questions as everyone has mentioned and the food was good.Here are a few questions I can remember
1)How would you rotate a binary number by a given amount in Verilog?
2)Divide by two/three circuit,draw state machine to do this task
3)There is a FIFO ,input is at 100MHZ output is at 80MHZ,At the input ,80 bits arrives every 100 cycles,what should be the size of FIFO so that no data is lost?
4)Questions on Setup,Hold,two's complement 5)A few basic questions on System verilog like assertions ,interfaces,mailboxes 6)Given seven binary numbers each one bit ,a scheme to add them using minimum number of Full Adders 7)Program to reverse a string in any language you like ,program to find the missing numbers in an array (an array has 1,2,7,8 and the size of array is fixed so the missing numbers here would be 3,4,5,6,7,9 if size of array was 10 10)Reduction using k map,metastability issues
This could have been a very easy interview had I known it would be more Verilog and programming stuff.
Interview Question – Two or Three basic questions on power speed optimization in static CMOS Answer Question
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