Qualcomm Interview Questions in Raleigh-Durham, NC

Updated Jun 18, 2015
23 Interview Reviews

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  1.  

    SoC Verification Engineer Interview

    Anonymous Employee in Raleigh, NC
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 3 weeksinterviewed at Qualcomm (Raleigh, NC) in June 2015.

    Interview

    First 1:1 phone interview, Then an on site interview. In the onsite interview, three technical interviews separately in the morning, then having lunch with manager. In the afternoon, another technical interview and then talked with the manager of the manager.

    Interview Questions

    • First interviewer did bus connection verification. so he asked about the protocol of ahb and axi. Then he asked how many vip should be used for their verification environment. I didn't understand the question clearly. Because if we want to keep CPU and the code run on real CPU, we don't need to replace these interfaces with VIPs, but if the CPU needs to be replaced, only other slave/master interfaces need to be replaced by VIPs. After he cleared it, what he wanted to do was to replace all the CPU interfaces and other IP interfaces.
      The second interviewer asked 2 questions: 1) how to check the module was reset by reading/writing registers? The premise for this was there was no spec for register. 2) how to check an interrupt was generated? There was a bit in the register for the interrupt signal.
      The third interviewer asked the following questions: 1) virtual memory structure 2) spin lock 3) tomasulo 4) fibonacci generator
      The last technical interviewer asked: 1) shell questions: search a key word in a file and count how many lines contain the key word 2) Perl sort question: user perl to sort a hash with key or with value 3) set environment variable in Perl 4) fibonacci generator 5) there are 2 buckets: 5 litters and 3 litters, how to get 4 litters of water 6) there is a rectangle pie, remove a small rectangle in that large rectangle, after that, use a straight line to cut the pie to get 2 equal areas.
      There was another question I forgot who asked: use SystemVerilog to generate address with the following constraint: 0x0 (mem1), 0x4(mem2), 0x8(mem3), 0xC(mem1), 0x10(mem2), 0x14(mem3) ...
       
      2 Answers
  2. Helpful (2)  

    CPU Verification Interview

    Anonymous Employee in Raleigh, NC
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied through a recruiter. The process took 4+ weeksinterviewed at Qualcomm (Raleigh, NC) in May 2015.

    Interview

    I applied through a recruiter and got email to set up a phone interview after 1 month, interview was pretty simple and basic questions about computer architecture like what is a pipeline, what are hazards in the pipeline and stages in the pipeline. How to test 32 bit adder using assembly language. Waiting for the response.

    Interview Questions

    • cpu hazard?
      pipeline?
      stages of pipeline?
      how to test 32 bit adder?
       
      Answer Question
  3.  

    Digital Design Engineer Interview

    Anonymous Interview Candidate in Raleigh, NC
    Accepted Offer
    Positive Experience
    Difficult Interview

    Application

    I applied online. The process took 2+ monthsinterviewed at Qualcomm (Raleigh, NC) in March 2015.

    Interview

    Phone interview followed by on-site three weeks later. They were designing their own transaction protocol based on the AMBA AXI/ACE spec. I was fortunate to have studied the same for two months for directed research under a professor. I could tackle AXI questions. Interview went well. Didn't nail it but not too bad. Got a verbal offer three weeks later. Got the formal letter 1.5 weeks after the verbal.

    Few details:
    1. Had interview with three panels consisting of 2-4 members each.
    2. Questions on bus architecture, synthesis, protocols, verilog, and certain design problems.
    3. 1 major design question by each panes, takes 15-20 mins to solve; related to logic design--flip-slops, decoders, etc.

    Interview Questions

    • What are the channel in AXI and ACE? What is cache coherency?   Answer Question
    • Design a variable size decoder in Verilog.   1 Answer
    • DDR2 initialization engine synthesis issues (from my resume).   Answer Question

    Negotiation

    Tried to negotiate, but they denied my request suggesting they have standard packages for New Graduates. However, the pay is higher than the industry standard so not a big issue.

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  5.  

    Physical Design Engineer Interview

    Anonymous Employee in Raleigh, NC
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online – interviewed at Qualcomm (Raleigh, NC) in February 2015.

    Interview

    Was very straight forward. easy rounds. Static Timing Analysis, Timing Closure. Synthesis, Clock Tree Synthesis, Floor planning, Place and Route, RTL and netlist synthesis. Questions based on projects, PERL, Clock Tree Distribution, Power and Ground area, Die area

    Interview Questions

  6. Helpful (1)  

    Digital ASIC Design Engineer Interview

    Anonymous Employee in Raleigh, NC
    No Offer
    Negative Experience
    Difficult Interview

    Application

    I applied through a recruiter. The process took 2+ monthsinterviewed at Qualcomm (Raleigh, NC) in August 2014.

    Interview

    Started with a Recruiter contacting me via LinkedIn. An exchange of resume lead to a phone interview with the hiring manager and a technical team member. The phone conversation went well, conversation flowed, questions were discussed both technical and leadership, and what is sometimes a 15 minute planned conversation went on pleasantly for an hour. An invitation for an on-site interview was extended. Travel planning went smoothly, all via email. My hotel was just down the road from the offices, so I had no problem arriving early to the interview. The start time had been delayed multiple times, so each meeting was very short, clipping discussions and making design-on-the-fly tasks very difficult. Lunch with the hiring manager and another team member, was very nice, pleasant and relaxed, even though more technical questions came up in the conversation. I submitted my trip expenses, and was informed in a confirmation email, that it could take up to 90 days for reimbursement. I'm still waiting, and it's been 80 days.

    Interview Questions

    • Given a white-board diagram of a block with a FIFO, and verbal description of the block's inputs & outputs, write on the withe board the Verilog or SystemVerilog for the design. I had 15 minutes. Why would you want someone who goes straight to code, with no planning? That usually results in spaghetti code that has to be rewritten.   Answer Question
    • White-board diagram of a block with one input pin (+ clock), and one output pin. The input is a serial stream of data. The output =1 whenever the pattern "0110" has been seen on the serial data. Everything is synchronous to the clock input. Write the Verilog. Given the shortened time constraint for the interview, diagram the design solution. In addition to what you come up with, write a bubble diagram for an FSM solution.   1 Answer
  7. Helpful (2)  

    SerDes Verification Interview

    Anonymous Employee in Raleigh, NC
    Declined Offer
    Positive Experience
    Difficult Interview

    Application

    I applied through a recruiter. The process took 6+ weeksinterviewed at Qualcomm (Raleigh, NC) in April 2014.

    Interview

    Got a phone call first. Basic concentration was on testbench experience, work experience, how u develop an tb, uvm/ovm basics, testplaning basics, pci express knowledge, work exp

    i did very well but they took >30 days to get back. invited for an onsite interview.
    it lasted for 6 rounds
    first round: Clock domain crossing issues, how to solve, what to do if it's a bus, design a fsm, divide by 2,3 behavioural codes using shift registers, meta stability, how u solve, how u model it in env
    2) CDC, pcs layer, pci express school project, phy layer questions how u implement in behavioural modeling, tb architecting questions, CDC fifo questions, block level model. why 8b/10b encoding in pcie, how signalling is done, ltssm questions
    3) SV, basics, verilog basics, delays waveforms, timing, fixes, other stupid questions which didn't make much sense. his answers were very theoretical not a practical applications.
    4)same questions from previous rounds. more concentration on how pcie device works, various layers, test planing, tb development, execution related questions, more technica questions
    5) lunch. behavioural, my experience in varuos senarios
    6)same questions from prev rounds. my environment questions, uvm, sv questions, perl codes, pll questions, phy related questions

    good interview process. grilled every aspect. but decioson making is insane. i did extremly well but they still didn't get back and i had another offer. team members were very nice

    Reasons for Declining

    very slow process and had better job and offer

  8. Helpful (1)  

    Staff Verification Engineer Interview

    Anonymous Interview Candidate in Raleigh, NC
    Accepted Offer
    Positive Experience
    Difficult Interview

    Application

    I applied online. The process took 3+ monthsinterviewed at Qualcomm (Raleigh, NC) in February 2014.

    Interview

    Applied through the Qualcomm Career section in Sept and did not get any communication for more than 2 months. Out of the blue got a call from HR wanting to schedule a Phone Screen, and within a couple of day I was Phone screened. Phone screen was really stimulating, lots of questions regarding ASIC verification, Memory Management, Cache Coherency and FPGA based emulation, Palladium/Veloce emulation flow and using emulation for Simulation Acceleration. It was a nice 2 way discussion which made it real fun, lasted about 45 minutes. Told next day, they wanted to setup an onsite, but since it was around X'mas, we were not able to schedule the interview till early Jan. The team was very flexible in terms of interviewing as I fell sick and had a planned vacation, due to which I wasnt able to interview till mid-Feb.

    The Onsite was short in duration but concentrated in content. Welcomed by my manager and was taken to a conference room, where I had 2 1 hour group interviews with 4 people each. 1st hour was related to my resume and emulation experience more relevant to my role and the 2nd hour was general ASIC verification questions with a team of 4 sr Staff level engineers. Got an offer a week later, but due to a relocation, working out the logistics took almost another month before I could join. Very slow process overall. There were 2 stages of reference checks, first after the phone screen and 2nd after the onsite, before the offer was made. There was no HR or personality interview, only technical interviews.

    Interview Questions

    • Questions regarding STA mode and Transactor based Simulation Acceleration:
      How would you implement a transactor? Use SystemC or System Verilog and why? How will you communicate between the DUT and the transactor testbench? Explain the PCIe speedbridge interface and how would you debug it?
       
      Answer Question

    Negotiation

    A couple of rounds of negotiation and I was able to get the desired package, though, there was some flexibility in terms of the benefits.

  9. Helpful (4)  

    Verification Engineer Interview

    Anonymous Employee in Raleigh, NC
    No Offer
    Negative Experience
    Average Interview

    Application

    I applied through a recruiter. The process took 2 weeksinterviewed at Qualcomm (Raleigh, NC) in January 2014.

    Interview

    Phone interview, then invited to come on-site. Had to fly from California for the interview and take two days off from work. Interview consisted of a surprise panel. I was not told the details beforehand of who I was meeting so, when I got there, I was surprised by a panel of 5 people. I did really well in spite of being blindsided like that. Everyone was nice and I answered all the questions and conducted myself well (I'm comfortable talking to a group). Next, they sent in another panel to grill me on coding, problem solving, OVM, and other technical validation/verification questions. I answer all of them and when it is over, the hiring manager asks to speak with me one on one. I think he's going to ask about salary requirements, however he asks me how much RTL debug experience I have. I tell him openly that I debug at the interface level, where components connect to a fabric for instance.

    Later that day I get an email saying they were looking for someone with more design and RTL debug experience. I was confused since I never claimed to have that specific expertise and was very open about that. They could have asked me over the phone and saved a lot of time.

    Interview Questions

    • How do you verify connectivity of an interface to memory with 6 bits of address and 6 bits of data? Show me a program that will write, read, and verify the connectivity.   1 Answer
  10.  

    Cpu Verification Engineer Interview

    Anonymous Employee in Raleigh, NC
    No Offer
    Positive Experience
    Easy Interview

    Application

    I applied online – interviewed at Qualcomm (Raleigh, NC) in May 2013.

    Interview

    The whole interview process was divided into two part, First level was basic questions on projects, Brief project explanation. After he moved on to basic question on Pipelining, Caches,Forwarding, hazard detection and example of hazard. The Second interview was much more detailed on Level having OoO processing, Scheduling and bits of coding skills.

    Interview Questions

    • He asked me How to test a 32 bit adder....Well I said under the circumstances that we have the netlist we can use ATPG to get it done or match it with another perfect adder netlist. he didnt seem to be satisfied.   Answer Question
  11.  

    Analog/Mixed Signal Design Engineer Interview

    Anonymous Interview Candidate in Raleigh, NC
    Accepted Offer
    Difficult Interview

    Application

    I applied online. The process took 2+ monthsinterviewed at Qualcomm (Raleigh, NC) in April 2013.

    Interview

    I submitted my resume online, got an email a week later from HR to schedule an interview. Got invited onsite and interviewed with the only 3 analog designer staff engineers there. If they read this, they would probably know it was me sharing the review. A week later I got 4 more phone interviews by people from San Diego (that's where the rest of the team is). Phone and onsite interviews were purely technical. The last phone interview is from HR, just describing what will happen next and also asked me about the other offer I had (since I brought up that I have a deadline for it). Asked about salary expectations and that's it. A week later I followed up with my HR contact since my deadline for the other offer I have is coming up. I was told unofficially that they are putting together an offer from me. During that time I was asked for verification I am enrolled in a graduate program in the US and was asked to give email addresses for references. True enough, they emailed my references. After that, I got a call about the official offer.

    Interview Questions

    • Everything is technical, but maybe simple. Admittedly, I don't know every answer, but I tried to analyze things and just get through the quesitons. This is the most technical interview I had ever experienced during my job search.   Answer Question

    Negotiation

    I did not negotiate because a friend in San Diego got the same offer package and considering the difference in the cost in living between SD and Raleigh, I thought it was fair enough. Also, it was better than the other offer I had and just honestly a good offer for a first job for a new PhD grad.

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