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Synopsys Engineering Interview Questions & Reviews

All Interviews Received Offers

Getting an Interview  

55%
33%
11%

Interview Experience  

83%
0%
16%

Interview Difficulty  

Average Difficulty
6 candidate interviews Back to all interview questions
Relevance Date Difficulty
in

Declined Offer

Positive Experience

Average Interview

Engineering Interview

Engineering
Hillsboro, OR

I applied through an employee referral and the process took a day - interviewed at Synopsys in May 2012.

Interview Details – The phone screen was light weight, just background check and so on. The onsite interview was a little bit more serious. The first talk was with 2 heads (one is the boss of the group and one is his boss). Both were pretty friendly without deep technical questions. Then there were 4 2-1 or 3-1 interviews, each 1 hour. Most were technical and some are tough. Covering algorithms / C++ knowledges / behavioral questions. I answered 80% of them.

Interview Question – What happened when a function is called in C++?   Answer Question


1 person found this helpful

Accepted Offer

Positive Experience

Difficult Interview

Engineering Interview

Engineering

I applied online and the process took 5 days - interviewed at Synopsys in June 2010.

Interview Details – Graph algorithms, probability

Interview Question – Topological sort   Answer Question

Negotiation Details – Not good ..I didn't have choice


5 people found this helpful

No Offer

Positive Experience

Difficult Interview

Engineering Interview

Engineering

I applied through an employee referral and the process took 1+ week - interviewed at Synopsys in June 2009.

Interview Details – Sometime back i interviewed for a position at a big MNC. I would like
to share my interview with you so that you can know the questions that
interviewer ask these days. Position i was looking for was a Backend
Design Engineer (logic syn, PV etc).
Here are some question which i remember.

1.) Optimize 2 input inverting mux (D1 connected to A, D2 tied low and
Select tied to B)
2.) Solve the following using Boolean logic.
a. O = A + B[(AB+B) + AB’]
3.) Draw circuit for the following logic.

If tag{3:0} == adr(3:0)
        Then (
                Match = 1
                )
        Else
                (
                Match = 0
                      )
End
4.) What is setup and hold and what factors determine setup and
holdtime calculation for a flop.
5.) What is PV and how does it impact the timing of a chip
6.) What happens to power if voltage drops. Tell me the equation of
static and dyn power.
7.) What is noise and RV and how to fix it
8.) What is spacing and shielding and when to prefer either of two.
9.) What determines the metal pitches for a particular process
technology.

there were more however do not remember now.
will post more once it comes to mind.

The part after STA, FV, CTS would be ASIC Place/ Route.

Few companies would hire specifically for ASIC Place/ Route work.

So, Students should concentrate more on Front-end design part of ASIC
Design. [HDL, testbenches and after some experience students get an
opportunity to do logic synthesis, STA, FV and other front-end tasks.

I think, more new-college-grads are chosen for Front-end design part
of ASIC Design than Back-end.

Once again, dont worry too much about all steps in detail [as a new
college grad]
Remember concepts are important; rattling off specific tool commands
may NOT show your understanding of the tool.
For example,

1] What are various compile strategies?
Which strategy should be used when?
think of all the variables involved, top-down, bottom-up, small-
design, large-design, constraints already defined, tight constraints,
loose constraints, is it a new design OR migration from earlier
design?
I can understand you may NOT be able to think of all the variables
BUT the key here is to "let the interviewer know HOW YOU THINK"

Remember that the interview questions are generic concentrating on
fundamentals.

always ask the questions like why and how that phenomenon happens. If
the phenomenon is happening some particular way, [may be the way you
do NOT want it to happen, then see how to improve that thing ; So,
first you will have to think why it is happening that way and is there
a better way to do it]
Targeting above sentence to VLSI point of view; THINK OF all VLSI
Qns with that approach; area/ speed tradeoff, WHY does textbook say
that critical input should be connected closer to output, 2bit-line
SRAM versus 1 bit-line SRAM tradeoff.

If you can explain it clearly to yourself, any interview will be piece
of cake.


No Offer

Negative Experience

Average Interview

Engineering Interview

Engineering

I applied through an employee referral and the process took a day - interviewed at Synopsys in January 2011.

Interview Details – Got email, asking to setup a phone interview. Took about 1 hour. Was asked to describe my Ph.D.

Interview Question – What "static" refers in C to?   Answer Question


Declined Offer

Positive Experience

Average Interview

Engineering Interview

Engineering

The process took a day - interviewed at Synopsys in October 2010.

Interview Details – screening phone interview by a senior manager first followed by 4-5 rounds of technical discussins

Interview Question – given a recursive call u have to trace it functioning   Answer Question


No Offer

Positive Experience

Average Interview

Engineering Interview

Engineering
Bangalore (India)

I applied through a recruiter and the process took a day - interviewed at Synopsys in October 2009.

Interview Details – There was a phone interview to start with, followed by a call to attend a series of face-to-face interviews. The phone interview was basically a discussion of what the job was about, but the on-site interviews were fairly technical. Questions included C/C++, and some puzzles. The questions were not too demanding.

Interview Question – How would you handle a potential disagreement with your manager?   Answer Question

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