I applied through other source and the process took a day - interviewed at Xilinx in October 2011.
Interview Details – Interviewed with PCIe team. Female engineer from Colorado asked me a reasonable nested loop question then proceeded to interrupt me at least 8 times. After the 5th interruption I gave up solving the problem and did my best not to make a scene. She continued to interrupt me then asked very condescending questions in a very sarcastic tone. I have never met, seen, or heard of a more disrespectful interviewer during my time as a professional engineer. I later met an engineer from Xilinx (Malaysia) who worked with this woman and confirmed my assessment of her. In my opinion there was an additional engineer who was insulting. He asked me very simple questions then finished with a trick question that I didn't realize until the interview was over. I'm certain that I have designed more async interfaces than the entire team combined but I'm sure he told everyone that I missed the trick async question since he insisted on taking a picture of my solution. They were typical arrogant engineers. I couldn't be more please to not be working for this team. Lastly, the position was for a SystemVerilog OVM verification engineer working on PCIe gen 3. NOT one single question on systemverilog, OVM, or PCIe. Not one.
I applied online and the process took 2+ weeks - interviewed at Xilinx.
Interview Details – It is very exhausting. 9 interviews . but the interviews were fair.
Interview Question – None Answer Question
Negotiation Details – not much to negotiate
Interviewed at Xilinx
Interview Details – Many script related questions (such as perl, unix, etc). Need some basic understanding of fpga/logic design
Interview Question – some brain teasers Answer Question
All Programmable and Smarter Systems For more than 25 years, Xilinx's (NASDAQ: XLNX) core competency has been the development of programmable technologies starting with the introduction of the first FPGA. Today’s… — Full Overview
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