Circuit Designer Interview Questions

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“Why there is a pinch-off during saturation mode of a CMOS device?”

“How would you draw the CMOS schematic for a 2-input NAND gate? What would the pull-up and pull-down networks look like? If VDD and VSS are switched, what gate is formed?”

“How would you size the NMOS and PMOS transistors in an inverter to obtain equal rise and fall times?”

“How would you design your own synthesis tool ?”

“Stack of 2 N transistors connected between VDD and VSS. Calculate the voltage in the mid point if transistors equal in size. Gates both connected to VDD.”

“How much experience did I have designing DMMs”

“why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc”

“C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question)”

“They asked things like if the source of NMOS is open, what is the voltage at the source if the gate and drain at 3 and 5V. If the gate of inverter is connected through a resistor to a output, what is...”

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