Component Design Engineer Interview Questions

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“Design an FSM that can generate a single pulse after certain no. of rising clk edge. Such no. is defined by the input.”

“Was given a verilog code and was asked to guess the function of the module. It was a voltage controlled oscillator.”

“Diagram the frequency response of a signal after it has been passed through a 2X interpolation filter.”

“Voltage at the end of a stack of pass-transistors”

“Explain to me what an early clock is and on what edges you would like to clock the data on to avoid race conditions.”

“There was a BIG sheet of transistor layout and the interviewer wanted me to figure out the function.”

“What are the setup and hold violations and how to remove them?”

“Reverse a string, Reverse a linked list. Please check the description, I mentioned most of the stuff there.”

“What are write-back and write-through cache?”

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