View All num of num See all Photos Broadcom This employer has taken extra steps to respond to reviews and provide job seekers with accurate company information, photos, and reviews. Interested for your company?Learn More. www.broadcom.com Profile Unclaimed Overview Reviews Salaries Interviews Jobs Photos Benefits 1.0k Reviews 4.1k Salaries 399 Interviews Follow Add Review or Salary Follow Add Review or Salary Interview Question ASIC Design Engineer Interview Irvine, CA Broadcom how to generate a clock divide by 3 Tags: See more , See less 8 Answer Add Tags Answer Interview Answer 2 Answers ▲ 0 ▼ Assuming that input clock is square wave and 50% duty cycle,Method 1: Clk / 3 is equal to Clk / (6/2). this means fist divide by 6 and multiply by 2.dividing by 6( use two DFF(D is tied to Q_b and it is connected to clock of 2nd DFF).multiplying by 2( create some delay and XOR the two signals(the signal after dividing by 6 and its delayed signal), But it's hard to make the output clock have 50% duty cycle due to precise delay control. so alternative method 1 is first multiply by 2 and divide by 6.Method 2. Use 2 edge counters(one for rising edge and the other for falling edge)draw the state machine that goes (back) to toggle state when both counters become 2. Jong on Mar 8, 2013 ▲ 0 ▼ Sorry, Method 1 is incorrect.the possible method 1 is to delay the input clock and XOR the input clock and its delayed one(delay doesn't need to be precisely half period of input clock, which is good) then use a single rising edge counter to toggle when it counts 3 rising edges. this is glitch-free Jong on Mar 8, 2013 Add Answers or Comments To comment on this, Sign In or Sign Up.