Physical Design Engineer Interview Questions

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“You are give two flip-flops and there's an combination logic in between, the two flip-flops are driven by the same clock. You are provided with parameters of T_reg, T_logicmax, T_logicmin, T_setup...”

“You are provided with one XOR gate, one OR gate and one NOR gate. Please build a NAND gate.”

“CMOS Inverter , how to reduce the drive strength of Minimum size inverter”

“How to modify a two-input NAND gate to an inverter?”

“Draw an inverter. Then switch the position of NMOS and PMOS. Describe the circuit.”

“DCG related, how to fix timing? Verilog RTL case x, case z, DFF, Dlatch Perl scripting TCL scripting in PT ICC Design patitioning”

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“Draw a two-put NAND gate and size it, assuming the ratio of PMOS/NMOS is 2 in inverter. Then suppose two input are A and B for NMOS and PMOS. A is close to output and B is close to ground, input A...”

“Why do you want to relocate from India to US”

“VLSI lower power design techniques, FSM sequence detection, transistor layout, combinational circuit design, timing (setup, hold time), floorplanning, noise, crosstalk”

“Difference Between SRAM and DRAM”

110 of 41 Interview Questions