Senior ASIC Design Engineer Interview Questions

(Posted anonymously by job candidates)

7 Companies: 13 of 7

Intel Corporation Interviews

1 Senior ASIC Design Engineer Interview Question and Review

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Link A Media Devices Interviews

1 Senior ASIC Design Engineer Interview Question and Review

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LSI Interviews

1 Senior ASIC Design Engineer Interview Question and Review

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7 Interview Questions: 17 of 7 Sort by  

Jun 20, 2014

Interview Question for Senior ASIC Design Verification Engineer at AMD:

“(Unexpected) What the types of caches?”

Jun 5, 2014

Interview Question for Anonymous at Marvell Technology:

“The interview was straight forward and aveage”

Sep 9, 2013

Interview Question for Anonymous at Intel Corporation:

“Nothing really, some pros/cons of different physical verification tools, how to filter through 100k+ errors, how to solve chip level LVS issues. Should be easy for experience engineers to answer.”

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Apr 23, 2013

Interview Question for Anonymous at Link A Media Devices:

“design async-fifo and sync-fifo in circuit level”

Jul 26, 2009

Interview Question for Senior ASIC/FPGA Design Engineer at Honeywell:

“Can't remember.”

Jun 15, 2009

Interview Question for Anonymous at Applied Micro Circuits:

“which is hard to fix -- setup violation or hold violation? And why?”

Jun 15, 2009

Interview Question for Anonymous at Applied Micro Circuits:

“FIFO questions; how do you calculate enough FIFO size when the input rate is N, and the output rate is M.”

Glassdoor is your free inside look at Senior ASIC Design Engineer interview questions and reviews. All interview questions posted anonymously by employees and interview candidates.