Senior Verification Engineer Interview Questions
(Posted anonymously by job candidates)
8 Companies: 1–3 of 8
AMD Interviews
2 Senior Verification Engineer Interview Questions and Reviews
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NetLogic Microsystems Interviews
1 Senior Verification Engineer Interview Question and Review
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NVIDIA Interviews
1 Senior Verification Engineer Interview Question and Review
See the latest NVIDIA Jobs
See all companies matching Senior Verification Engineer (8)
| 17 Interview Questions: 1–10 of 17 | Sort by |
Mar 27, 2012
Interview Question for Senior ASIC Verification Engineer at Synaptics:
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“Full adder circuit, FIFO, Capacitance effect, C, Verilog” |
Apr 11, 2011
Interview Question for Senior Verification Engineer at Cavium Networks:
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“Linked List and Binary Search trees” |
Feb 15, 2011
Interview Question for Senior Verification Engineer at Telegent Systems USA:
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“What are the different types of synchronizers and their function?” |
Feb 15, 2011
Interview Question for Senior Verification Engineer at Telegent Systems USA:
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“Design a circuit for edge detection circuit” |
Aug 29, 2010
Interview Question for Senior Verification Engineer at SmartPlay:
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“difference between active and passive agents?” |
Aug 29, 2010
Interview Question for Senior Verification Engineer at SmartPlay:
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“testbench structure for a random testbench?” |
Aug 23, 2010
Interview Question for Senior SoC Verification Engineer at ASTC:
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“Asking abut the technical question.” |
Jan 29, 2010
Interview Question for Senior Hardware Verification Engineer at NVIDIA:
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“There are 5 bowls with 100 candies each. In 4 bowls, all of the candies are 10 grams each. In 1 bowl, all the candies are 9 grams each. Using a digital scale, how can you determine which bowl has the 9 gram candies by using only 1 weighing?” |
