Senior Verification Engineer Interview Questions

(Posted anonymously by job candidates)

9 Companies: 13 of 9

NVIDIA Interviews

6 Senior Verification Engineer Interview Questions and Reviews

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AMD Interviews

3 Senior Verification Engineer Interview Questions and Reviews

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NetLogic Microsystems Interviews

1 Senior Verification Engineer Interview Question and Review

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17 Interview Questions: 110 of 17

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Aug 10, 2014

Interview Question for Senior Design Verification Engineer at Marvell Technology:

“A question about managing branching methodology when dealing with IP cores.”


Jun 20, 2014

Interview Question for Senior ASIC Design Verification Engineer at AMD:

“(Unexpected) What the types of caches?”


Apr 24, 2014

Interview Question for Senior Design Verification Engineer at NVIDIA:

“There were no difficult questions.”


Apr 8, 2014

Interview Question for Senior Verification Engineer at Oracle:

“Given an async fifo, tell the testplan --> complicated fifo with lot of requirements..(writes are done by 3 masters. there is an arbiter).”


Apr 8, 2014

Interview Question for Senior Verification Engineer at Cadence Design Systems:

“nothing specific”


Mar 29, 2014

Interview Question for Senior Verification Engineer at STMicroelectronics:

“random, depends on team”


May 29, 2013

Interview Question for Senior Verification Engineer at NVIDIA:

“The hour-long interview was mostly about the current projects.”


Jan 30, 2013

Interview Question for Senior Verification Engineer at PLX Technology:

“There was no really difficult question. If I remember clearly, maybe questions on RTL coding style, like
always @(posedge clk, reset_active) begin
if(reset_active)
   do somthing
else
   do…”


Oct 2, 2012

Interview Question for Senior Staff Verification Engineer at Broadcom:

“FIFO sizes and uses. Design question on clock-domain-crossing and clock synchronizers”


Sep 13, 2012

Interview Question for Senior ASIC Verification Engineer at NVIDIA:

“Design an arbiter. This was detailed and went on for the whole 45+ mins.”