SRAM design engineer Interview Questions

(Posted anonymously by job candidates)

3 Companies: 13 of 3

Qualcomm Interviews

1 SRAM design engineer Interview Question and Review

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NVIDIA Interviews

1 SRAM design engineer Interview Question and Review

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Dolphin Technology Inc Interviews

1 SRAM design engineer Interview Question and Review

See the latest Dolphin Technology Inc Jobs

6 Interview Questions: 16 of 6 Sort by  

Apr 27, 2013

Interview Question for Circuit Design Engineer(SRAM Memory Or High Speed IO) at Dolphin Technology Inc:

“Flip Flops and setup hold time and Max Frequency of a sequential and Combinational circuit”

Apr 27, 2013

Interview Question for Circuit Design Engineer(SRAM Memory Or High Speed IO) at Dolphin Technology Inc:

“why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc”

Apr 27, 2013

Interview Question for Circuit Design Engineer(SRAM Memory Or High Speed IO) at Dolphin Technology Inc:

“C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question)”

Apr 27, 2013

Interview Question for Circuit Design Engineer(SRAM Memory Or High Speed IO) at Dolphin Technology Inc:

“He drew digital circuits with basic Gates and the delays and asked to draw waveforms”

Oct 9, 2011

Interview Question for SRAM Circuit Design Engineer at Qualcomm:

“Difference between 6T and 8T sram cell
transistor operating regions in general, and then specifically for inverter
reverse body biasing in detail - what happens at transistor and device level…”

Feb 25, 2009

Interview Question for SRAM design engineer at NVIDIA:

“12V source in series with 3 caps of so and so capacitance, the last of which is hooked to gnd. If node between the first and 2nd cap is initially open, then closed, what are the node voltages.”

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