SRAM Design Engineer Interview Questions

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“12V source in series with 3 caps of so and so capacitance, the last of which is hooked to gnd. If node between the first and 2nd cap is initially open, then closed, what are the node voltages.”

“why PMOS is slower than NMOS, questions on computing output of a circuit having complex NMOS pass gate connections etc”

“Why there is a pinch-off during saturation mode of a CMOS device?”

“C questions sheet ( 5 questions including questions on binary tree, difference between ++var and var++, sorting question)”

“He drew digital circuits with basic Gates and the delays and asked to draw waveforms”

“Difference between 6T and 8T sram cell
transistor operating regions in general, and then specifically for inverter
reverse body biasing in detail - what happens at transistor and device level…”

“Flip Flops and setup hold time and Max Frequency of a sequential and Combinational circuit”

18 of 8 Interview Questions