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Qualcomm ASIC Design Engineer Interview Question

I interviewed in San Diego, CA and was asked:
"what 's the steps of synthesis?"
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The process of mapping the HDL code to cells using technological libraries according to the specified design constraints is known as synthesis.
1. The desired HDL code, the technological libraries and the environmental constrains are send to the synthesis tool and then it does further optimization accordingly
2.Translates the passed HDL to Boolean Logic
3. Maps the Boolean logic into hiearchial blocks and the blocks to equivalent cells
4.Optimizations are generally power, area and performance trade offs. It also does timing optimizations like adding buffers to clear off hold time violations and uses different cells of the same functionality to meet the set up-hold requirements.
- Swetha on Sep 10, 2013 Flag Response

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