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66 asic physical design engineer jobs in San Jose

SENIOR ASIC POWER ENGINEER

Nvidia 100+ Reviews Santa Clara, CA

- Architect and develop power estimation models for dynamic use-case, leakage, and IO power estimation. Design tools based on these models, and… Experteer

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ASIC Engineer 3

Juniper Networks Sunnyvale, CA

Design and simulate clock, power and repeater circuits at the transistor level Layout clock, repeater and power cells using physical compiler… Experteer

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Technical Lead - Systems Software/Hardware Engineering

Cisco Systems 100+ Reviews San Jose, CA

● Analyze customer setup test bed, apply customer configuration to reproduce customer issue for both hardware & software. ● Investigation failure… Glassdoor

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Staff Low Latency ASIC Design Engineer

Juniper Networks 100+ Reviews Sunnyvale, CA

• Develop the architecture and micro-architecture for the next generation ASICs with special emphasis on low latency • Set Methodology for Low… Glassdoor

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Technical Lead - System Failure Analysis engineer

Cisco Systems 100+ Reviews San Jose, CA

● Analyze customer setup test bed, apply customer configuration to reproduce customer issue for both hardware & software. ● Investigation failure… Glassdoor

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Staff Digital Design Engineer – easy apply

InvenSense 6 Reviews San Jose, CA

• Define and implement RTL designs for MEMS sensor systems, optimized for low power and area. • Synthesis and timing analysis of the block level… Glassdoor

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Design Automation Engineer (Staff/Prinicpal)

SK Hynix Memory Solutions 8 Reviews San Jose, CA

Requirements: BS/MS in Electrical Engineering. 5 to 10 years of work experience. Strong knowledge of ASIC EDA design flow and methodology: Physical… Glassdoor

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Place and Route Manager

Altera 100+ Reviews San Jose, CA

will include but are not limited to the following: • Management of Place and Route at block and chip level • Custom Clock Tree / Clock Tree… Glassdoor

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Staff ASIC Design Engineer – new

Name Confidential Milpitas, CA

Knowledge in physical aware synthesis flows, low power flows including multi-Vt, multi-voltage synthesis & power gating insertion (UPF/CPF) in… Glassdoor

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Engineer, Staff Physical Design

marvell 100+ Reviews Santa Clara, CA

○ Solid knowledge on static timing analysis (PrimeTime), EM/IR-Drop/crosstalk analysis (Celtic, PTSI, Apache, AstroRail), formal or physical… Glassdoor

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Engineer, Physical Design

marvell 100+ Reviews Santa Clara, CA

* Formal or physical verification (Formality, Verplex, Calibre, Hercules) a plus. As a key member of central physical design team, you will provide… Glassdoor

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Principal Physical Design Engineer – new

Name Confidential San Jose, CA

include the place and route implementation , STA analysis , physical verification of high speed SOCs, clock structures and high speed memory and I/O… Glassdoor

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Staff Low Latency ASIC Design Engineer – new

Name Confidential Sunnyvale, CA

 Develop the architecture and micro-architecture for the next generation ASICs with special emphasis on low latency Set Methodology for Low… Glassdoor

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Sr. Staff Chip Integration Engineer

Broadcom 100+ Reviews San Jose, CA

We are looking for bright, motivated, innovative, and hardworking engineers to join our top notch engineering team. You will work closely with… Glassdoor

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Sr. Staff ASIC Engineer / Design Lead For Low Latency Design – new

Name Confidential Sunnyvale, CA

Develop the architecture and micro-architecture for the next generation ASICs with special emphasis on low latency Set Methodology for Low Latency… Glassdoor

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SR. PHYSICAL DESIGN / TIMING ENGINEER

Name Confidential Santa Clara, CA

- Implementation, timing convergence, and signoff of large-scale high-frequency low-power ASIC, CPU, and/or GPU designs at block level, cluster… Glassdoor

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Front-End Application Engineer - ICD/FED – new

Name Confidential San Jose, CA

The primary focus of the Senior Applications Engineer is to support the sale and adoption of Cadence Front-End products to help Chip Designer… Glassdoor

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Staff ASIC Design Engineer

SanDisk Milpitas, CA

BSEE or MSEE with a thorough understanding of ASIC and FPGA implementation and development, with minimum 10 +years of experience Project/TeamLead… Experteer

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SR. PHYSICAL DESIGN / TIMING ENGINEER

Nvidia 100+ Reviews Santa Clara, CA

- Implementation, timing convergence, and signoff of large-scale high-frequency low-power ASIC, CPU, and/or GPU designs at block level, cluster… Experteer

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