MIPS Technologies has a full time position open for a Design Verification Engineer. This position will focus on the verification of next-generation MIPS processor cores. Verification tasks assigned to this position cover the full product development cycle: supporting the definition of the verification methodology for a specific project or project components, specifying the verification testbench as required, owning and developing major verification blocks including: stimulus generators, monitors and checkers (scoreboards), creating a testplan and generating tests and coverage code to support it, ensuring closure of the coverage metrics and developing scripts as needed to analyze results, check coverage and drive regressions, etc.

This position requires an MS/BSEE or equivalent, plus three or more years of applicable experience in the verification of high performance microprocessor systems. The successful candidate will possess strong knowledge in HDL/programming languages (Verilog, C/C++), RTL and logic simulators, HVLs like VERA or e or System Verilog, plus general scripting skills with Perl/Python or equivalent. The ability to write MIPS assembly language diagnostic code to support verification efforts is highly desirable. General knowledge of microprocessor architecture is required (pipelines, out-of-order, superscalar and caches); prior experience with MIPS processors, experience with multiple issue cores and knowledge in constrained random verification (OVM, UVM, VMM) is preferred.

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