AMD ASIC Design & Verification Engineer interview questions

ou have an asynchronous FIFO (in RTL) to transfer data between two clock domains (Clk_A and Clk_B). Describe how you would verify this FIFO. What testbench components would you build? What corner cases would you include? How would you write assertions? How would you verify that metastability / synchronization issues are handled?

What did you do at your previous co-op employer?