Ambarella Interview Questions in San Jose, CA | Glassdoor

Ambarella Interview Questions in San Jose, CA

13 Interview Reviews

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13 Candidate Interview Reviews Back to all Interviews

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  1.  

    ASIC Verification Engineer Interview

    Anonymous Interview Candidate in Sunnyvale, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 2+ weeks. I interviewed at Ambarella (Sunnyvale, CA) in March 2016.

    Interview

    Two step process, 1. Phone interview, easy question 45 minutes.
    2. On-site 4 sessions 1 hr each
    The interview experience was good, It was paid trip onsite and they took very good care of me.

    Interview Questions


  2.  

    Software Architecture Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Easy Interview

    Application

    I applied through a recruiter. The process took 2 weeks. I interviewed at Ambarella (Santa Clara, CA) in September 2014.

    Interview

    Connected via a recruiter who had placed another candidate in the same group. Drove to Santa Clara campus on 3 different days to interview with a total of 5 people (the entire group), plus an internal HR person.
    I found the people very friendly and had a good vibe about the company. I breezed through the interviews and found them to be not terribly technically challenging. However, I am a long-time computer architect with detailed hardware modeling experience, and I believe they want a more software-centric person.

    Interview Questions

    • Question dealing with I/O in C++. This does not come up very often in hardware modeling.   1 Answer

  3. Helpful (3)  

    ASIC Verification Intern Interview

    Anonymous Interview Candidate in Santa Clara, CA
    Declined Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 3 weeks. I interviewed at Ambarella (Santa Clara, CA) in January 2014.

    Interview

    I applied online. Received an interview call 2 weeks later.
    I was informed that the position requires knowledge of computer architecture, digital design and C/C++. I was asked 1 question in each topic. 1 question on cache associativity, 1 question to design a circuit which outputs a pulse when an input flips, 1 question each on virtual functions and recursive functions (Factorial series).
    I was informed there would be a follow-up interview, but I was given the offer without the second interview.

    Interview Questions

    • Design a circuit which outputs a pulse when the input flips. The input is synchronous to a clock.   1 Answer

    Reasons for Declining

    Received a better offer elsewhere.


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  5. Helpful (1)  

    Entry Level ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online. I interviewed at Ambarella (Santa Clara, CA) in September 2013.

    Interview

    two round short onsite.
    Second round is simple, all common ASIC interview questions.
    First round mainly about asynchronize fifo and a tricky latch decoder question.
    Failed in the first one but still got the second chance, got rejected after the second one although didn't make any mistake.

    Interview Questions


  6.  

    Analog Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer

    Application

    I applied online. The process took 2 days. I interviewed at Ambarella (Santa Clara, CA).

    Interview

    The Interviewer just asked about the project in your resume:
    the company need someone who can use verilog, and understand the layout of your design.
    No hiring entry-level engineer


  7.  

    Summer Intern-Summer Intern Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied through college or university. The process took 4+ weeks. I interviewed at Ambarella (Santa Clara, CA) in February 2013.

    Interview

    Submitted resume at the career fair, and then get e-mails to have phone interview. Three rounds of phone interviews.

    Interview Questions

    • 1. Basic circuit design and logic design question
      2. Basic verilog question (e.g. verilog module to swap 2 variables, 4-to-1 mux etc.)
      3. Write a verilog testbench module which generates 2 output signals:
          1) clock - at 1GHZ
          2) reset - asserted (1) for first 100 cycles and then deasserted (0)
      4. 8 entry FIFO module
      5. What are the 2 components of a chip power and how will you reduce each one?  
      Answer Question

  8.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Average Interview

    Application

    I applied online. The process took 2 days. I interviewed at Ambarella (Santa Clara, CA) in January 2013.

    Interview

    Initially applied online and got email for interview. They seems to tend to interview local candidates so I am told to drop by their office directly. It is an 1-hour interview with several questions which include state machine, sorting, and testing. ASIC design is really different from Analog. Huge programming skills are required.
    Nice people there.

    Interview Questions

    • 1. sequence detector
      2. get second largest number of a unsorted array
      3. setup and hold time
      4. some testing questions.  
      Answer Question

  9.  

    Analog Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Neutral Experience
    Difficult Interview

    Application

    The process took 2+ weeks. I interviewed at Ambarella (Santa Clara, CA) in November 2012.

    Interview

    I got a phone interview and after less than a week I was told to arrange an on-site interview. Almost all interview questions are technical but basic. Familiarity to the topics and speed of response to those questions may be critical.Though the questions are not easy, the people interview me are quite kind.

    Interview Questions

    • 1. What are DNL and INL of an ADC? What's the difference?
      2. What's quantization noise? Derive signal-to-quantization-noise ration.
      3. How to compensate an OPAMP?
      4. When the size of tail current transistor increase, how will it affect the phase noise of a VCO?  
      Answer Question

  10. Helpful (1)  

    Logic Designer Interview

    Anonymous Interview Candidate in San Jose, CA
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied through college or university. The process took 1 day. I interviewed at Ambarella (San Jose, CA) in May 2012.

    Interview

    I met and talked with one of the VP on a campus recruiting event. The hiring process was described as consisting of an 1-hour phone screen interview and an 5-hour on-site interview by 5 interviewers. Everything should be very technical. The phone interview I had was almost purely technical with no chit-chat, with just a brief introduction then actually 30 minutes of problem solving. Need to be able to design logic gate circuits, both combinational and sequential. Need to know logic, diagrams, and coding. The company culture seems serious and fast-pace.

    Interview Questions

    • Design a single-bit-input, single-bit-output machine that outputs 1 when it recognizes the pattern 10110 and output 0 at all other times.   1 Answer

  11.  

    Engineering Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied online. The process took a week. I interviewed at Ambarella (Santa Clara, CA) in May 2012.

    Interview

    Ask me questions on my resume. Ask data structures and wrote a easy algorithm. and some architecture questions.

    Interview Questions


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