Intel Corporation ASIC Design Engineer Interview Questions | Glassdoor

Intel Corporation ASIC Design Engineer Interview Questions

5 Interview Reviews

Interview Experience

Interview Experience
50%
50%
0%

Getting an Interview

Getting an Interview
60%
20%
20%

Interview Difficulty

3.0
Average

Interview Difficulty

Hard

Average

Easy

5 Candidate Interview Reviews Back to all Interviews

Filter

Sort: Popular Date Difficulty

Filter

Sort: Popular Date Difficulty

Helpful (6)  

ASIC Design Engineer Interview

Anonymous Interview Candidate in Hillsboro, OR
No Offer
Positive Experience
Average Interview

Application

I applied through an employee referral. The process took a week. I interviewed at Intel Corporation (Hillsboro, OR).

Interview

I had a phone interview and was later called for an onsite interview. There were multiple positions available in various aspects of ASIC design, from RTL design, DFT, Physical Design etc.

They were testing my basics in each round. Basic questions on setup, hold time and special scenarios were given on the board and i was asked to solve them. What happens if nmos and pmos are inverted in an inverter. Basics on scan chains and Boundary Scan design (as it was on my course). Questions on synthesis, basic constraints in DC, like set_input_delay, set_output_delay, set_max_fanout, set_clock_latency.

FSM design and clock frequency divider ckts, by2 and by3. Later they asked 50% duty cycle in freq divided by 3 ckt. Asked me to code an up-down counter in verilog on white board. Asked about parameters and their usage in verilog. Asked some questions on synchronizing data signals between different clock domains.

Physical design round went a little unexpected. I was asked about what the properties of different metal layers might be. Which has higher cap and which has higher resistance. Other basic questions like clock skew and what is done to reduce clock skew. And some questions on various low power designs: power gating, clk gating, using low Vdd etc.

Interview Questions

  • I felt the most difficult question was about different metal layers and their properties   1 Answer

Other Interview Reviews for Intel Corporation

  1. Helpful (2)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Hillsboro, OR
    No Offer
    Average Interview

    Application

    I applied online. The process took 2 weeks. I interviewed at Intel Corporation (Hillsboro, OR) in May 2012.

    Interview

    45min phone interview, followed by a 5 hour on-site interview

    Interview Questions

    • List all possible ways to minimize the power dissipation of an ASIC chip.   2 Answers
  2.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Hillsboro, OR
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied online. The process took 1 day. I interviewed at Intel Corporation (Hillsboro, OR) in March 2012.

    Interview

    Applied online.
    1:1 phone interview.
    general questions not technical details.

    Interview Questions

  3.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Folsom, CA
    No Offer
    Neutral Experience
    Easy Interview

    Application

    I applied online. The process took 2+ weeks. I interviewed at Intel Corporation (Folsom, CA) in July 2011.

    Interview

    I was contacted by email for phone interview for a senior ASIC Design Engineer position. The phone interview went alright (took place for about an hour and 20 mins). The interviewer was nice and asked me many technical questions which I answered. At the end of the interview he asked me when I can appear for an on-site interview.

    So.. I went for an on-site interview about 10 days later. This on-site interview process was the part that seemed very strange (and also not right) to me. It turned out that they call a whole bunch of candidates for interview on the same day. There are two batches of interviewees - morning and afternoon. I was selected for the morning batch (starts at 9am). The first half hour was a presentation about the group. It had all the candidates sitting together. Now most of these candidates were RCGs. I think I was the only senior level person in that group. After that the interviewees had 4 rounds of interviews, each for 45 mins. I was very surprised that every single of those 4 interviews for me were conducted by VERIFICATION (not DESIGN) engineers and most questions were on verification. The questions were not difficult enough. It seemed to me that those questions were prepared with the RCGs in mind. I had no problem in answering them. In any case, all the interviewers were nice and friendly. However, every single one of them asked me what kind of position I am interested in - design or verification. Now, my resume said very clearly that I am a design engineer and looking for similar position - so I didn't really understand the reason for ambiguity.

    After the technical interviews were over at noon, the candidates had to come back to the same conference room. We were told to help ourselves for lunch with some food that was waiting for us in the same room. No going out for lunch or anything. The food (very few items, I could just have salad and breads) was poor. Never before have I seen a company doing this to interview candidates. The whole setup seemed very unprofessional. What is even more ridiculous is that I did not even get to meet the hiring manager for the position. Come on... what is the point of an on-site interview then?

    About 3 business days later I got an email that I was not selected. I was a bit disappointed because I don't think I did badly in the interviews, however I wouldn't call it a huge surprise either going by the unprofessional and wrong interview process. When I am not even questioned on the area of work for the opening, that certainly raises questions about the fairness and credibility of the interview and selection process.

    Interview Questions

  4. Is this helpful? The community relies on everyone sharing – Add Anonymous Interview Review


  5. Helpful (3)  

    ASIC Design Engineer Interview

    Anonymous Employee in Ahmedabad (India)
    Accepted Offer
    Positive Experience
    Difficult Interview

    Application

    I applied through college or university. The process took a week. I interviewed at Intel Corporation (Ahmedabad (India)) in April 2011.

    Interview

    F2F. Came for internship in college.The student which were having pointer more than 8 wer nly eligible. It was a good exp. They are askin question on every subject. RTL Verification CMOS Timing.

    Interview Questions

    • Mainly focused on Low power as I said I am interested in low power. Asked about timing analysis STA setup hold and synthesis. Some basic rtl design with verilog vhdl.Basic CMOS modeling NAND gate and NOR gate. IN HR round as i was fail in one of the subject was asking about that subject but as i performed well they consider that.   1 Answer
Don't Miss Out On a Job You Love
Upload a resume to easily apply to jobs from anywhere. It's simple to set up.