Intel Corporation Signal Integrity Engineer, Serial Interconnects, DDRx Interview Questions | Glassdoor

Intel Corporation Signal Integrity Engineer, Serial Interconnects, DDRx Interview Questions

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Signal Integrity Engineer, Serial Interconnects, DDRx Interview

Anonymous Interview Candidate in Hillsboro, OR
No Offer
Positive Experience
Difficult Interview

Application

The process took 1 day. I interviewed at Intel Corporation (Hillsboro, OR) in July 2011.

Interview

It all started out with a phone interview with the hiring manager of the group. The second phone interview was mainly technical topics to gauge my level of expertise on a wide variety of topics, in general Signal Integrity topics, S parameters, overshoot, undershoot, timing, some statistical analysis.

Next was the offer for an onsite interview in Hillsboro with the team which was set up for July 18th, 2011. The process was very easy; call American Express travel, set up the flight, hotel, car. Intel also mails a prepaid Visas for incidental expenses before, during, and after the actual interview. I flew in July 17th (Sunday), chilled out for a day, and the onsite started promptly at 9:00AM Monday morning.

The interview consisted of 6 hours of techical topics and a one hour lunch with the hiring manager which was more of a behavioral/personality type of session. The first 5 technical interviewers, many of whom had a masters, and some possibly PHD, was very thorough and deep and consisted of a variety of topics, some only peripherally related to the Signal Integrity position. The interview took place in one conference room with a large whiteboard available, which I filled completely with drawings, equations, etc. 6 times.

I also think part of the psychology in the interview is little things like the first interviewer being late to pick me up and a last minute substitute for one of the interviewers that was a PCIe timing/clock guru. His questions were the most difficult due to lack of significant experience in that particular area.

Questions included:

1. S Parameters, S Parameters, Also, one of the guys pulled out Z parameters, just for fun
2. Jitter spectrum
3. PLL Bandwidth in a PCIe clock recovery circuity
4. FEXT and NEXT
5. Power plane noise and decoupling
6. Draw a CMOS inverter and explain why the driving high/low impedances are different
7. PCIe common clock architecture and why there's a 12ns delta between the common clock to the transmitter and the total length of the receiver common clock plus the TX lane length
8. General questions on some of the projects I have worked on, board design, simulations, measurements, etc.
9. This was a good one. A differential pair is routed as a microstrip and the weave of the FR4 causes the er on one of the signals in the pair to vary a lot from the other member of the pair (think egregious, 3.4 on one, 4.5 on the other). What effects can you expect and what can you do to mitigate. Great question.

Then the oddball question, which Intel, Google, etc tosses out to gain insight into your thought process. My question was: How many full time piano tuners work in Seattle?

My advice to prospective interviewees; brush up on all of your basics, get the job description and polish your presentation on all of the skills required. My impression was that you don't have to know everything about every question, but they want to make sure you have at least a fair depth of knowledge and experience in the main job requirement areas. Above all things, don't try to bluff your way through a topic that you don't know about; just say you don't know because if you're trying to BS your way through it, they'll figure that out immediately. And if you don't understand a question, ask for more details.

And don't be too nervous; everyone was very friendly and very professional. Dress code is business casual but I saw many Intel employees with shorts, tee shirts. It's pretty laid back dress code wise however during the interview, I'd recommend you spiff up somewhat to at least shirt and dockers, a tie wouldn't hurt.

The reason I didn't get an offer, which the hiring manager graciously shared with me, was that most of the interviewers felt I did a good to great job on the various topics during the interviews and I had a wide breadth of valuable experience on the topics discussed, but I didn't have the depth of experience and knowledge that they were seeking for the position advertised.

Interview Questions

  • Why does the PCIe spec limit the time skew of a common clock architecture to less than 12 ns skew between the clock routed to the transmitter side and the sum of the clock routed to the receiver side PLUS the routing length of the TX lane to the receiver.   1 Answer
  • A differential pair is routed as a microstrip and the weave of the FR4 causes the er on one of the signals in the pair to vary a lot from the other member of the pair (think egregious, 3.4 on one, 4.5 on the other). What effects can you expect and what can you do to mitigate.   1 Answer
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