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Marvell Semiconductor ASIC Design Engineer Interview Questions

Interviews at Marvell Semiconductor

46 Interview Reviews

Experience

Experience
44%
42%
14%

Getting an Interview

Getting an Interview
53%
22%
14%
11

Difficulty

3.0
Average

Difficulty

Hard
Average
Easy

 

ASIC Design Engineer Interview

Anonymous Interview Candidate
No Offer
Positive Experience
Average Interview

Interview

strong background knowledge required. staffs on the resume

Interview Questions

Other Interview Reviews for Marvell Semiconductor

  1. Helpful (1)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate
    No Offer

    Application

    The process took 1 day. I interviewed at Marvell Semiconductor.

    Interview

    I was offered 2 phone interview. And then have an onsite interview. They pay for the flight and hotel. Their interviews are quite difficult. In the 1st phone, they asked to describe MESI's all transition on phone. And most question is on CPU design. They asked a lot of implementation details.

    Interview Questions

    • They asked a lot questions on pipeline design. Like how to optimize the overall ipc regarding branch? Is it possible to get branch resolved in decode stage?   Answer Question

  2.  

    ASIC Design Engineer Interview

    Anonymous Employee in Santa Clara, CA
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 4 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in September 2011.

    Interview

    First of all, the recruiter just reach me through the email. And then we went through one-round technical phone interview, including asking me something about the asic flow, verilog. About two weeks later, I got a notification that I passed the phone round, and we reserved a skype interview including 4 rounds. 4 rounds include basic concepts and some verilog coding.

    Interview Questions

  3. Helpful (4)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    Declined Offer
    Positive Experience
    Average Interview

    Application

    I applied through an employee referral. The process took 2 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in September 2015.

    Interview

    The first round was a phone interview of around 45 minutes. Focused entirely on linear pipeline and Out of Order Pipeline principles. The second round was a face to face interview at Santa Clara. 4.5hrs of interview (45 minutes per interviewer), was completely technical focussing on FSm, Verilog design, Cache and Tomasulo Out of order implementation.

    Interview Questions

    • 1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines.
      2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design.
      One of the interviewers gave a scenario and asked to wite a code to validate the integrity of the circuit (to test our VERIFICATION thinking ).   Answer Question

  4.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Ann Arbor, MI
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied online. The process took 1+ week. I interviewed at Marvell Semiconductor (Ann Arbor, MI) in August 2015.

    Interview

    I apply online for intern. It took around 10 days to get the email to tell I took 30 min interview for the intern. The question is all about cache part. I didn't prepare very well. Some question I answered is not quite well.

    Interview Questions


  5.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied through an employee referral. The process took a week. I interviewed at Marvell Semiconductor (Santa Clara, CA) in December 2014.

    Interview

    phone interview -- just general question because i got refer from my friends
    onsite interview -- got me email from HR to arrange my interview date and time
    i had 5 people for interview
    most of them were nice, but one guy was very annoying. i coudn't understand his question, so i asked again. but he was angry because i asked again.
    had a lunch with them and talk about general question

    Interview Questions

    • clock divider / mealy vs moor fsm / through my resume project / setup time hold time   Answer Question

  6.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Neutral Experience
    Difficult Interview

    Application

    I applied online. The process took 2 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in November 2014.

    Interview

    apply online and after several weeks, I got phone interview. It is about ASIC design/verification. My background is more focus on Verification of microprofessor, FPGA. Not very familiar with ASIC flow.so it is very important for background match.

    Interview Questions


  7. Helpful (1)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Negative Experience
    Average Interview

    Application

    I applied online. The process took 3+ months. I interviewed at Marvell Semiconductor (Santa Clara, CA) in November 2014.

    Interview

    I received a call for an onsite interview as I was in Santa Clara itself. I gave first onsite with 3 engineers. After 15-20 days I received call for another onsite with 4 engineers. The interviews were pretty basic stuff related to Verilog basics, FSM Design, FIFO related questions as well as on the resume. After 2nd onsite I waited for 2 months but I did not get any reply from HR or recruiter. Finally when I contacted manager, I was told that they had already selected some other candidate. They seriously should learn some professionalism and have the courtesy to give an update to someone who gave 2 onsite interviews. Totally disappointed with the process speed as well communication.

    Interview Questions

    • Verilog tasks and functions, FSM Design, FIFO Depth, some system verilog questions.   1 Answer
  8. Helpful (1)  

    ASIC Design Engineer Interview

    Anonymous Employee
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied online. I interviewed at Marvell Semiconductor.

    Interview

    Phone interview for very basic digital design question i.e. setup/hold time, max clock frequency, and some project questions. Received onsite interview after 2 weeks, asked very detailed on my verilog project, fsm, fifo, cross domain clock, little perl and OOP.

    Interview Questions

    • never learned perl before so did not answer.   1 Answer

  9. Helpful (2)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clarita, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 3 weeks. I interviewed at Marvell Semiconductor (Santa Clarita, CA) in January 2016.

    Interview

    I have applied this position on line last year . I have received a phone interview last week and there will be a phone interview this week. Asked the basic questions about the ASIC design and questions about the resume. Clock skew and jitter.Blocking and nonblocking. Setup and hold time question. Some basic question about the DFT. STA.

    Interview Questions

    • Describe the basic flow of DFT and the problem you met in the project   Answer Question

See What Marvell Semiconductor Employees Are Saying

StarStarStarStarStar     Former Senior Software Quality Engineer

Pros: “You can climb up the ladder if you have the skills.”“You can climb up the ladder if you have the skills.” – Full Review

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