Marvell Semiconductor ASIC Design Engineer Interview Questions in San Jose, CA | Glassdoor

Marvell Semiconductor ASIC Design Engineer Interview Questions in San Jose, CA

16 Interview Reviews

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Helpful (3)  

ASIC Design Engineer Interview

Anonymous Interview Candidate in Santa Clara, CA
Declined Offer
Positive Experience
Average Interview

Application

I applied through an employee referral. The process took 2 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in September 2015.

Interview

The first round was a phone interview of around 45 minutes. Focused entirely on linear pipeline and Out of Order Pipeline principles. The second round was a face to face interview at Santa Clara. 4.5hrs of interview (45 minutes per interviewer), was completely technical focussing on FSm, Verilog design, Cache and Tomasulo Out of order implementation.

Interview Questions

  • 1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines.
    2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design.
    One of the interviewers gave a scenario and asked to wite a code to validate the integrity of the circuit (to test our VERIFICATION thinking ).   Answer Question

Other Interview Reviews for Marvell Semiconductor

  1.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied through an employee referral. The process took a week. I interviewed at Marvell Semiconductor (Santa Clara, CA) in December 2014.

    Interview

    phone interview -- just general question because i got refer from my friends
    onsite interview -- got me email from HR to arrange my interview date and time
    i had 5 people for interview
    most of them were nice, but one guy was very annoying. i coudn't understand his question, so i asked again. but he was angry because i asked again.
    had a lunch with them and talk about general question

    Interview Questions

    • clock divider / mealy vs moor fsm / through my resume project / setup time hold time   Answer Question

  2.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Neutral Experience
    Difficult Interview

    Application

    I applied online. The process took 2 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in November 2014.

    Interview

    apply online and after several weeks, I got phone interview. It is about ASIC design/verification. My background is more focus on Verification of microprofessor, FPGA. Not very familiar with ASIC flow.so it is very important for background match.

    Interview Questions

  3.  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Negative Experience
    Average Interview

    Application

    I applied online. The process took 3+ months. I interviewed at Marvell Semiconductor (Santa Clara, CA) in November 2014.

    Interview

    I received a call for an onsite interview as I was in Santa Clara itself. I gave first onsite with 3 engineers. After 15-20 days I received call for another onsite with 4 engineers. The interviews were pretty basic stuff related to Verilog basics, FSM Design, FIFO related questions as well as on the resume. After 2nd onsite I waited for 2 months but I did not get any reply from HR or recruiter. Finally when I contacted manager, I was told that they had already selected some other candidate. They seriously should learn some professionalism and have the courtesy to give an update to someone who gave 2 onsite interviews. Totally disappointed with the process speed as well communication.

    Interview Questions

    • Verilog tasks and functions, FSM Design, FIFO Depth, some system verilog questions.   1 Answer

  4. Helpful (3)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied through a recruiter. The process took 2+ weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in March 2014.

    Interview

    one phone interview, asked about projects on the resume. Then asked about MESI protocol. Then Onsite interview. There are 5 people. First one asked basic CPU questions, such as 5 stage pipelined CPU. Second one asked me about reorder buffer in the out of order processor and load store queue. Third one asked about waveform questions. The last two asked me about some verilog questions.

    Interview Questions


  5. Helpful (1)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Negative Experience
    Easy Interview

    Application

    I applied online. The process took 1 day. I interviewed at Marvell Semiconductor (Santa Clara, CA) in December 2012.

    Interview

    Online applications and call within 2-4 weeks. Strange thing manager called directly without scheduling an interview and started asking all sorts of questions. He was so impressed that towards the end he said the next round might be bypassed and HR might send the on-site invitation. Till date, I haven't heard back from them neither the HR nor the manager who called.


  6.  

    ASIC Design Engineer Interview

    Anonymous Employee in Santa Clara, CA
    Accepted Offer
    Average Interview

    Application

    I applied online. I interviewed at Marvell Semiconductor (Santa Clara, CA).

    Interview

    I was called for a phone interview first, talk about my previous experience, mainly about my resume, and ask some simple digital circuit question. One week after, I was scheduled for a screen interview, with 5 interviewers, last more than 3 hours.
    They asked some small questions, one guy still focus on the resume, some others ask some verilog question, some design question, quite straight-forward.

    Interview Questions

    • All the questions are clear and normal. eg. write FSM in verilog, some DFT related questions.   Answer Question

    Negotiation

    No negotiation


  7. Helpful (1)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Negative Experience
    Average Interview

    Application

    I applied online. I interviewed at Marvell Semiconductor (Santa Clara, CA).

    Interview

    Interview process was straightforward. Phone interview followed by onsite with 6 1:1: interviews.

    All basic design question from VLSI, datapath design and bus architectures.

    The interview went well, but they have a simple policy of not responding to any emails under any pretext. I am under the assumption that I was not selected due to their strong inkling to be completely ignorant to my emails.

    At this point I have no regard for a company that treats candidates so poorly; it just shows the amount of respect (or lack of) that they have for people in general.

    Interview Questions

  8. Helpful (3)  

    ASIC Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied through an employee referral. The process took 2 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in July 2012.

    Interview

    1.Frequency divider by 3
    2.MUX finish AND,OR,XOR,XNOR function
    3.Simple STA problem
    4.FSM to detect 11011
    5.detect how many logic 1 in circuit level
    6.Bubble pushing problems
    7.FIFO working function

    Interview Questions

    • There are 8 bits inputs ,only use full adder to detect how many logic 1's   2 Answers

  9. Helpful (7)  

    ASIC Design Engineer Interview

    Anonymous Employee in Santa Clara, CA
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied through an employee referral. The process took 1 day. I interviewed at Marvell Semiconductor (Santa Clara, CA) in September 2011.

    Interview

    Clock domain crossing
    verilog about the differences between blocking/non- blocking assignments
    points you list on your resume
    basic ALU questions
    Truth table and k-maps
    frequency divider and counters
    DFF with synchronized reset and asynchronized reset verilog codes
    FIFO synchronized and asynchronized

    Interview Questions

    Negotiation

    nothing is negotiable


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