Marvell Semiconductor Logic Design Engineer Interview Questions | Glassdoor

Marvell Semiconductor Logic Design Engineer Interview Questions

Interviews at Marvell Semiconductor

9 Interview Reviews

Experience

Experience
66%
17%
17%

Getting an Interview

Getting an Interview
57%
43%

Difficulty

3.0
Average

Difficulty

Hard
Average
Easy

 

Logic Design Engineer Interview

Anonymous Employee in Santa Clara, CA
Accepted Offer
Positive Experience
Average Interview

Application

I applied through college or university. The process took 4+ weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in March 2012.

Interview

First phone interview, then on-site interview. In the onsite interview, five engineers interviewed me and two of them are managers/project leads. Each interview took 45 minutes. The process was smooth and the accommodation was good. I had a lunch there. The food is good. After a month, I received the offer in phone,

Interview Questions

  • The interview covers static timing analysis and optimization, verilog coding, logic design puzzles like using MUX to achieve XOR gate.   Answer Question

Other Interview Reviews for Marvell Semiconductor

  1. Helpful (2)  

    Logic Design Engineer Interview

    Anonymous Employee in San Jose, CA
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied through college or university. The process took 3 weeks. I interviewed at Marvell Semiconductor (San Jose, CA) in February 2016.

    Interview

    My resume was referred to CPU group through an alumni from umich. Around 1 months after I submitted my resume, I got an email from the hiring manager. He asked me what was the good day for the phone interview. The phone interview took half an hour. One logic engineer asked me some basic questions about 5 stage in order pipeline and something about my resume. After 2 weeks came the invitation for onsite interviewIt. It took half day for meeting 5 people. Each interviewer spent ~ 30 minutes and asked ~ 5 questions. Each interviewer asked questions in the different areas.

    Interview Questions

    • Do we need PC to index second level table of branch predictor (i.e. pattern history table)? Why? What if bits of PC more than bits to index to pattern history table?   1 Answer
    • How can we use PRF to implement CMOV instruction?   1 Answer

  2.  

    Logic Design Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Average Interview

    Application

    I applied online. The process took 4+ weeks. I interviewed at Marvell Semiconductor.

    Interview

    First HR sent an email asking about general questions like work authorization and relocation. It's preview inquiry. Then if you are qualified they will contact you within two weeks. You will answer the email's questions and tell HR more about yourself to be qualified to the job. After that it's the phone call interview.

    Interview Questions

    • Question about verilog function and task, the functionality and difference   1 Answer
  3. Helpful (1)  

    Logic Design Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Difficult Interview

    Application

    I applied online. I interviewed at Marvell Semiconductor.

    Interview

    phone interview about 30 mins

    Interview Questions

    • Asked about FIFO, cache, pipeline, Computer architecture, logic design, testbench   Answer Question

  4.  

    Logic Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    Declined Offer
    Easy Interview

    Application

    I applied through college or university. The process took 4 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in October 2013.

    Interview

    Campus interview first during the career fair time. Followed by a phone interview one week after and scheduled onsite one week after. I heard back from the HR person after one week of my onsite. Great campus, nice people, fancy cafe.

    The CPU group is a mix of design and verification. Average difficulty for the questions, some recruiters are also from the verification team.

    Interview Questions

    • How to apply what we learned from school to the current going on project?
      Some verilog coding questions.
      Basic logic design questions.

      More on the verilog project we did at school for a RISC processor.   Answer Question

    Reasons for Declining

    Have other offers.


  5. Helpful (1)  

    Logic Design Engineer Interview

    Anonymous Employee
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied online. I interviewed at Marvell Semiconductor.

    Interview

    Heard about job openings through a friend that was contacted by a recruiter. E-mailed my resume to the recruiter and was invited for short on-site interviews with two different teams: CPU logic design and SoC verification. I was only brought on-site for the first step because I was living in Santa Clara at the time.

    After the two interviews, I was later invited back for a full day of on-site interviews with the CPU team. I interviewed with 5 different members of the CPU team. I thought I did really well with the interviews but it still took Marvell weeks to get back to me with an official offer.

    Interview Questions

    • Questions were related to logic design and computer architecture. With a good understanding of pipeline design and out-of-order execution principles the questions were not too hard. The only question that I couldn't really solve was about the design of a scalable, fair arbiter. Expect questions about out-of-order execution algorithms, state machine design, and logic optimization.   Answer Question

    Negotiation

    I was a new college graduate and did not negotiate. I had a competing offer for a higher salary though, so that helped.


  6.  

    Logic Design Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Positive Experience
    Average Interview

    Interview

    I got a phone interview the other day directly from a current employee from their CPU group. He asked me about the basic concepts in computer architecture and it was not very hard. Also, he asked a lot about work experiences showed on my resume.

    Interview Questions


  7.  

    Logic Design Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Negative Experience
    Average Interview

    Application

    I applied online. The process took 2 weeks. I interviewed at Marvell Semiconductor (Santa Clara, CA) in March 2013.

    Interview

    CPU group
    1 phone 1 onsite
    Met 6 people including hr.
    most interviewers were nice except for one guy.
    This guy was eating snack and playing with whatever in his hands when I was solving problems.
    Not sure they really wanted to hire or just bored at their daily work

    Interview Questions

  8. Helpful (2)  

    Logic Design Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Neutral Experience
    Average Interview

    Application

    I interviewed at Marvell Semiconductor in July 2012.

    Interview

    Phone interview followed by an onsite interview..The position was in the CPU logic design team. Phone interview was basic with questions related to pipeline concepts, FIFO design, cache coherency protocols.
    Onsite interview consisted of 5 rounds - 2 logic design, 3 computer architecture


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