Marvell Technology Verification Engineer Interview Questions | Glassdoor

Marvell Technology Verification Engineer Interview Questions

21 Interview Reviews

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  1.  

    ASIC Verification Engineer Interview

    Anonymous Interview Candidate
    No Offer

    Interview

    A manager call me and give me a phone interview, the questions are not difficult but his accent is too heavy which make me saying pardon all the time... it lasts about 30 mins, and after that he let me ask some questions, and what I asked is if a verification engineer find a bug, who is responsible to fix it, the verification engineer or the designer? what he answered is the verification will report it then ask the designer to fix

    Interview Questions

    • how do you know you have cover all the case in your testbench   Answer Question

  2.  

    Verification Engineer Interview

    Anonymous Interview Candidate
    No Offer
    Average Interview

    Application

    I applied online. I interviewed at Marvell Technology.

    Interview

    applied online. HR passed my resume to a group, probably a senior engineer set a phone interview. The feedback is okay, but I haven't heard anything further from it yet.

    Interview Questions

    • It was a group dealing with timing, so basically some tools related to timing analysis.   Answer Question

  3.  

    Design Verification Engineer Interview

    Anonymous Interview Candidate
    No Offer

    Interview

    I applied online. They gave me two phone interviews of two positions. The first one is logic design position, the questions are all about computer architecture: branch predictor, forward, pipeline, what is cache, cache coherence, etc. For the first interview, I was asked about more than 15 questions. Lucky, I spent 3 hours reading the CA book before interview. For the design verification interview, I haven't prepared at all since I didn't know that it was a verification position, all the questions about programing were not answered well. It has been three weeks since the interview, I received no responses.

    Interview Questions

    • For the design verification interview, I haven't prepared at all since I didn't know that it was a verification position, all the questions about programing were not answered well.   Answer Question

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  5. Helpful (1)  

    ASIC Verification Engineer Interview

    Anonymous Employee in Santa Clara, CA
    Accepted Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 4+ weeks. I interviewed at Marvell Technology (Santa Clara, CA) in December 2013.

    Interview

    The entire process took about a month. Two phone interviews followed by an onsite interview. Environment was very friendly. Basics of Comp. Arch., Perl, Verilog and OOPs asked.

    Interview Questions


  6. Helpful (1)  

    Design Verification Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied through an employee referral. The process took a week. I interviewed at Marvell Technology (Santa Clara, CA) in July 2013.

    Interview

    Referred by the employee in the group. It takes only 1 week to proceed. Most people are nice. The interview takes 8 hours including 1 hour for lunch. You must be prepared.

    Interview Questions


  7. Helpful (3)  

    Accepted Offer

    Application

    I applied online. I interviewed at Marvell Technology.

    Interview

    1 telephonic interview followed by 2 on site interviews.

    Interview Questions

    Negotiation

    No negotiation


  8. Helpful (1)  

    ASIC Verification Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Easy Interview

    Application

    I applied online. The process took a week. I interviewed at Marvell Technology (Santa Clara, CA) in October 2012.

    Interview

    Contacted by hiring manager and got arranged a phone interview a week later. First self-introduce. Then got asked four technical questions. Clock frequency divider, digital circuit design- given 4 inputs, outputs and timing diagram to design gate level circuits, Verilog question about signed and unsigned integer... The interviewer was very nice and asked me about my interest.

    Interview Questions


  9.  

    Design Verification Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Average Interview

    Application

    I applied online. The process took 2+ weeks. I interviewed at Marvell Technology (Santa Clara, CA).

    Interview

    Phone interview.

    Interview Questions

    • 1 is heavier than the other 5 marbles among 6 mables . given a weight to find the heavier one.   2 Answers

  10.  

    Verification Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Positive Experience
    Average Interview

    Application

    I applied online. The process took 2 weeks. I interviewed at Marvell Technology (Santa Clara, CA) in May 2012.

    Interview

    first a phone interview, then a screening interview with a hiring manager. If you pass this screening process, you'll get to meet with 5 or 6 engineers not necessarily from the same team. The technical interview takes about 3~4 hours.

    Interview Questions

    • 1. what's the difference between matlab function and matlab script?
      2. how does a system know when there is an error in the codeword?  
      Answer Question

  11. Helpful (2)  

    Design Verification Engineer Interview

    Anonymous Interview Candidate in Santa Clara, CA
    No Offer
    Neutral Experience
    Average Interview

    Application

    I applied online. The process took 1 day. I interviewed at Marvell Technology (Santa Clara, CA) in August 2011.

    Interview

    Initial phone screen (2) by hiring manager + junior employee (<3 years out of college).
    Manager asks conceptual and higher level questions. Junior employee asks coding questions (dictates a piece of code and asks questions on that (SystemVerilog)
    Have to fill out online profile and NDA before going onsite.
    Onsite interview start with meeting HR person who collects compensation information and asks questions like why you left each of your previous employers, why you are applying now, what other companies you are talking to, what factors you will use to decide the offer etc. Later met with hiring manager (heads design+verif), 1 design engineer and 2 verif engineers (junior+senior).
    Hiring Manager asks high level questions: e.g where will you place coverage collection for stimulus applied to DUT (monitor Vs driver)
    Junior verif person asks more coding questions and Behavioural interview (how to deal w/ diffcult person, failures in past etc)
    Design engineer asks some Verilog question and how to test a particular design.
    I give all of them an A for the interview.
    Other Sr Verif engineer was extremely challenged even to speak couple of sentences in English. He just thrust a piece of paper in front of me typed with a couple of questions. They had non standard terminology and despite repeated requests to explain the terms refused to do so. He kept repeating "just read the question and answer it". After some time I figured out what was the question and gave the answer. He claimed the answer was wrong and asked me to try again. After I came back I googled and found that my answer was correct. He could have moved on to additional questions and had a better/larger sample to make a decision, but stuck with the 2 questions throughout the 45 minute interview. This person should have been trained and lacked basic communication/interview skills in English.

    Be prepared for coding questions (some code w/ bug in it etc) regardless of how experienced you are.

    Interview Questions


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