Digital Design Engineer Interview
Verilog question with additional requirements. Design a FSM providing fibonacci sequence with enable and reset. Output should be immediate.
Two registers storing last two numbers in sequence with adding circuit muxed with the enable signal. Combinational output from mux. Answer should be in verilog code.
This is actually another way of asking: what is the difference of blocking and non blocking assignment. and the key point in this question is to use the non blocking assignment
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