Cover image for Cirrus Logic
Logo
See All Photos

Cirrus Logic

Engaged Employer

Cirrus Logic

Add an Interview

Interview Question

Digital Design Engineer Interview

-

Cirrus Logic

Verilog question with additional requirements. Design a FSM providing fibonacci sequence with enable and reset. Output should be immediate.

Interview Answers

2 Answers

0

Two registers storing last two numbers in sequence with adding circuit muxed with the enable signal. Combinational output from mux. Answer should be in verilog code.

Anonymous on

0

This is actually another way of asking: what is the difference of blocking and non blocking assignment. and the key point in this question is to use the non blocking assignment

answer on

Add Answers or Comments

To comment on this, Sign In or Sign Up.

Cirrus Logic Careers

Cover image for Cirrus Logic

Why Join Us? Is there a cooler semiconductor company on the planet? We’re hiring like mad right now, looking for the industry’s best...More

  • Perks
  • People
  • Awards
  • Giving Back
This is the employer's chance to tell you why you should work for them. The information provided is from their perspective.